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修訂1f00a56df6e04eec45a70a2bf5a4dea75c707e02 (tree)
時間2020-02-23 15:25:57
作者Yoshinori Sato <ysato@user...>
CommiterYoshinori Sato

Log Message

hw/char: RX62N serial communication interface (SCI)

This module supported only non FIFO type.
Hardware manual.
https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf

Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20190607091116.49044-8-ysato@users.sourceforge.jp>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Change Summary

差異

--- a/hw/char/Kconfig
+++ b/hw/char/Kconfig
@@ -46,3 +46,6 @@ config SCLPCONSOLE
4646
4747 config TERMINAL3270
4848 bool
49+
50+config RENESAS_SCI
51+ bool
--- a/hw/char/Makefile.objs
+++ b/hw/char/Makefile.objs
@@ -20,6 +20,7 @@ common-obj-$(CONFIG_SH4) += sh_serial.o
2020 common-obj-$(CONFIG_DIGIC) += digic-uart.o
2121 common-obj-$(CONFIG_STM32F2XX_USART) += stm32f2xx_usart.o
2222 common-obj-$(CONFIG_RASPI) += bcm2835_aux.o
23+common-obj-$(CONFIG_RENESAS_SCI) += renesas_sci.o
2324
2425 common-obj-$(CONFIG_CMSDK_APB_UART) += cmsdk-apb-uart.o
2526 common-obj-$(CONFIG_ETRAXFS) += etraxfs_ser.o
--- /dev/null
+++ b/hw/char/renesas_sci.c
@@ -0,0 +1,342 @@
1+/*
2+ * Renesas Serial Communication Interface
3+ *
4+ * Datasheet: RX62N Group, RX621 Group User's Manual: Hardware
5+ * (Rev.1.40 R01UH0033EJ0140)
6+ *
7+ * Copyright (c) 2019 Yoshinori Sato
8+ *
9+ * This program is free software; you can redistribute it and/or modify it
10+ * under the terms and conditions of the GNU General Public License,
11+ * version 2 or later, as published by the Free Software Foundation.
12+ *
13+ * This program is distributed in the hope it will be useful, but WITHOUT
14+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16+ * more details.
17+ *
18+ * You should have received a copy of the GNU General Public License along with
19+ * this program. If not, see <http://www.gnu.org/licenses/>.
20+ */
21+
22+#include "qemu/osdep.h"
23+#include "qemu/log.h"
24+#include "qapi/error.h"
25+#include "qemu-common.h"
26+#include "hw/hw.h"
27+#include "hw/irq.h"
28+#include "hw/sysbus.h"
29+#include "hw/registerfields.h"
30+#include "hw/qdev-properties.h"
31+#include "hw/char/renesas_sci.h"
32+#include "migration/vmstate.h"
33+#include "qemu/error-report.h"
34+
35+/* SCI register map */
36+REG8(SMR, 0)
37+ FIELD(SMR, CKS, 0, 2)
38+ FIELD(SMR, MP, 2, 1)
39+ FIELD(SMR, STOP, 3, 1)
40+ FIELD(SMR, PM, 4, 1)
41+ FIELD(SMR, PE, 5, 1)
42+ FIELD(SMR, CHR, 6, 1)
43+ FIELD(SMR, CM, 7, 1)
44+REG8(BRR, 1)
45+REG8(SCR, 2)
46+ FIELD(SCR, CKE, 0, 2)
47+ FIELD(SCR, TEIE, 2, 1)
48+ FIELD(SCR, MPIE, 3, 1)
49+ FIELD(SCR, RE, 4, 1)
50+ FIELD(SCR, TE, 5, 1)
51+ FIELD(SCR, RIE, 6, 1)
52+ FIELD(SCR, TIE, 7, 1)
53+REG8(TDR, 3)
54+REG8(SSR, 4)
55+ FIELD(SSR, MPBT, 0, 1)
56+ FIELD(SSR, MPB, 1, 1)
57+ FIELD(SSR, TEND, 2, 1)
58+ FIELD(SSR, ERR, 3, 3)
59+ FIELD(SSR, PER, 3, 1)
60+ FIELD(SSR, FER, 4, 1)
61+ FIELD(SSR, ORER, 5, 1)
62+ FIELD(SSR, RDRF, 6, 1)
63+ FIELD(SSR, TDRE, 7, 1)
64+REG8(RDR, 5)
65+REG8(SCMR, 6)
66+ FIELD(SCMR, SMIF, 0, 1)
67+ FIELD(SCMR, SINV, 2, 1)
68+ FIELD(SCMR, SDIR, 3, 1)
69+ FIELD(SCMR, BCP2, 7, 1)
70+REG8(SEMR, 7)
71+ FIELD(SEMR, ACS0, 0, 1)
72+ FIELD(SEMR, ABCS, 4, 1)
73+
74+static int can_receive(void *opaque)
75+{
76+ RSCIState *sci = RSCI(opaque);
77+ if (sci->rx_next > qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) {
78+ return 0;
79+ } else {
80+ return FIELD_EX8(sci->scr, SCR, RE);
81+ }
82+}
83+
84+static void receive(void *opaque, const uint8_t *buf, int size)
85+{
86+ RSCIState *sci = RSCI(opaque);
87+ sci->rx_next = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + sci->trtime;
88+ if (FIELD_EX8(sci->ssr, SSR, RDRF) || size > 1) {
89+ sci->ssr = FIELD_DP8(sci->ssr, SSR, ORER, 1);
90+ if (FIELD_EX8(sci->scr, SCR, RIE)) {
91+ qemu_set_irq(sci->irq[ERI], 1);
92+ }
93+ } else {
94+ sci->rdr = buf[0];
95+ sci->ssr = FIELD_DP8(sci->ssr, SSR, RDRF, 1);
96+ if (FIELD_EX8(sci->scr, SCR, RIE)) {
97+ qemu_irq_pulse(sci->irq[RXI]);
98+ }
99+ }
100+}
101+
102+static void send_byte(RSCIState *sci)
103+{
104+ if (qemu_chr_fe_backend_connected(&sci->chr)) {
105+ qemu_chr_fe_write_all(&sci->chr, &sci->tdr, 1);
106+ }
107+ timer_mod(sci->timer,
108+ qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + sci->trtime);
109+ sci->ssr = FIELD_DP8(sci->ssr, SSR, TEND, 0);
110+ sci->ssr = FIELD_DP8(sci->ssr, SSR, TDRE, 1);
111+ qemu_set_irq(sci->irq[TEI], 0);
112+ if (FIELD_EX8(sci->scr, SCR, TIE)) {
113+ qemu_irq_pulse(sci->irq[TXI]);
114+ }
115+}
116+
117+static void txend(void *opaque)
118+{
119+ RSCIState *sci = RSCI(opaque);
120+ if (!FIELD_EX8(sci->ssr, SSR, TDRE)) {
121+ send_byte(sci);
122+ } else {
123+ sci->ssr = FIELD_DP8(sci->ssr, SSR, TEND, 1);
124+ if (FIELD_EX8(sci->scr, SCR, TEIE)) {
125+ qemu_set_irq(sci->irq[TEI], 1);
126+ }
127+ }
128+}
129+
130+static void update_trtime(RSCIState *sci)
131+{
132+ /* char per bits */
133+ sci->trtime = 8 - FIELD_EX8(sci->smr, SMR, CHR);
134+ sci->trtime += FIELD_EX8(sci->smr, SMR, PE);
135+ sci->trtime += FIELD_EX8(sci->smr, SMR, STOP) + 1;
136+ /* x bit transmit time (32 * divrate * brr) / base freq */
137+ sci->trtime *= 32 * sci->brr;
138+ sci->trtime *= 1 << (2 * FIELD_EX8(sci->smr, SMR, CKS));
139+ sci->trtime *= NANOSECONDS_PER_SECOND;
140+ sci->trtime /= sci->input_freq;
141+}
142+
143+#define IS_TR_ENABLED(scr) \
144+ (FIELD_EX8(scr, SCR, TE) || FIELD_EX8(scr, SCR, RE))
145+
146+static void sci_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)
147+{
148+ hwaddr offset = addr & 0x07;
149+ RSCIState *sci = RSCI(opaque);
150+
151+ switch (offset) {
152+ case A_SMR:
153+ if (!IS_TR_ENABLED(sci->scr)) {
154+ sci->smr = val;
155+ update_trtime(sci);
156+ }
157+ break;
158+ case A_BRR:
159+ if (!IS_TR_ENABLED(sci->scr)) {
160+ sci->brr = val;
161+ update_trtime(sci);
162+ }
163+ break;
164+ case A_SCR:
165+ sci->scr = val;
166+ if (FIELD_EX8(sci->scr, SCR, TE)) {
167+ sci->ssr = FIELD_DP8(sci->ssr, SSR, TDRE, 1);
168+ sci->ssr = FIELD_DP8(sci->ssr, SSR, TEND, 1);
169+ if (FIELD_EX8(sci->scr, SCR, TIE)) {
170+ qemu_irq_pulse(sci->irq[TXI]);
171+ }
172+ }
173+ if (!FIELD_EX8(sci->scr, SCR, TEIE)) {
174+ qemu_set_irq(sci->irq[TEI], 0);
175+ }
176+ if (!FIELD_EX8(sci->scr, SCR, RIE)) {
177+ qemu_set_irq(sci->irq[ERI], 0);
178+ }
179+ break;
180+ case A_TDR:
181+ sci->tdr = val;
182+ if (FIELD_EX8(sci->ssr, SSR, TEND)) {
183+ send_byte(sci);
184+ } else {
185+ sci->ssr = FIELD_DP8(sci->ssr, SSR, TDRE, 0);
186+ }
187+ break;
188+ case A_SSR:
189+ sci->ssr = FIELD_DP8(sci->ssr, SSR, MPBT,
190+ FIELD_EX8(val, SSR, MPBT));
191+ sci->ssr = FIELD_DP8(sci->ssr, SSR, ERR,
192+ FIELD_EX8(val, SSR, ERR) & 0x07);
193+ if (FIELD_EX8(sci->read_ssr, SSR, ERR) &&
194+ FIELD_EX8(sci->ssr, SSR, ERR) == 0) {
195+ qemu_set_irq(sci->irq[ERI], 0);
196+ }
197+ break;
198+ case A_RDR:
199+ qemu_log_mask(LOG_GUEST_ERROR, "reneas_sci: RDR is read only.\n");
200+ break;
201+ case A_SCMR:
202+ sci->scmr = val; break;
203+ case A_SEMR: /* SEMR */
204+ sci->semr = val; break;
205+ default:
206+ qemu_log_mask(LOG_UNIMP, "renesas_sci: Register 0x%" HWADDR_PRIX
207+ " not implemented\n", offset);
208+ }
209+}
210+
211+static uint64_t sci_read(void *opaque, hwaddr addr, unsigned size)
212+{
213+ hwaddr offset = addr & 0x07;
214+ RSCIState *sci = RSCI(opaque);
215+
216+ switch (offset) {
217+ case A_SMR:
218+ return sci->smr;
219+ case A_BRR:
220+ return sci->brr;
221+ case A_SCR:
222+ return sci->scr;
223+ case A_TDR:
224+ return sci->tdr;
225+ case A_SSR:
226+ sci->read_ssr = sci->ssr;
227+ return sci->ssr;
228+ case A_RDR:
229+ sci->ssr = FIELD_DP8(sci->ssr, SSR, RDRF, 0);
230+ return sci->rdr;
231+ case A_SCMR:
232+ return sci->scmr;
233+ case A_SEMR:
234+ return sci->semr;
235+ default:
236+ qemu_log_mask(LOG_UNIMP, "renesas_sci: Register 0x%" HWADDR_PRIX
237+ " not implemented.\n", offset);
238+ }
239+ return UINT64_MAX;
240+}
241+
242+static const MemoryRegionOps sci_ops = {
243+ .write = sci_write,
244+ .read = sci_read,
245+ .endianness = DEVICE_NATIVE_ENDIAN,
246+ .impl = {
247+ .max_access_size = 1,
248+ },
249+};
250+
251+static void rsci_reset(DeviceState *dev)
252+{
253+ RSCIState *sci = RSCI(dev);
254+ sci->smr = sci->scr = 0x00;
255+ sci->brr = 0xff;
256+ sci->tdr = 0xff;
257+ sci->rdr = 0x00;
258+ sci->ssr = 0x84;
259+ sci->scmr = 0x00;
260+ sci->semr = 0x00;
261+ sci->rx_next = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
262+}
263+
264+static void sci_event(void *opaque, QEMUChrEvent event)
265+{
266+ RSCIState *sci = RSCI(opaque);
267+ if (event == CHR_EVENT_BREAK) {
268+ sci->ssr = FIELD_DP8(sci->ssr, SSR, FER, 1);
269+ if (FIELD_EX8(sci->scr, SCR, RIE)) {
270+ qemu_set_irq(sci->irq[ERI], 1);
271+ }
272+ }
273+}
274+
275+static void rsci_realize(DeviceState *dev, Error **errp)
276+{
277+ RSCIState *sci = RSCI(dev);
278+
279+ if (sci->input_freq == 0) {
280+ qemu_log_mask(LOG_GUEST_ERROR,
281+ "renesas_sci: input-freq property must be set.");
282+ return;
283+ }
284+ qemu_chr_fe_set_handlers(&sci->chr, can_receive, receive,
285+ sci_event, NULL, sci, NULL, true);
286+}
287+
288+static void rsci_init(Object *obj)
289+{
290+ SysBusDevice *d = SYS_BUS_DEVICE(obj);
291+ RSCIState *sci = RSCI(obj);
292+ int i;
293+
294+ memory_region_init_io(&sci->memory, OBJECT(sci), &sci_ops,
295+ sci, "renesas-sci", 0x8);
296+ sysbus_init_mmio(d, &sci->memory);
297+
298+ for (i = 0; i < SCI_NR_IRQ; i++) {
299+ sysbus_init_irq(d, &sci->irq[i]);
300+ }
301+ sci->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, txend, sci);
302+}
303+
304+static const VMStateDescription vmstate_rsci = {
305+ .name = "renesas-sci",
306+ .version_id = 1,
307+ .minimum_version_id = 1,
308+ .fields = (VMStateField[]) {
309+ VMSTATE_END_OF_LIST()
310+ }
311+};
312+
313+static Property rsci_properties[] = {
314+ DEFINE_PROP_UINT64("input-freq", RSCIState, input_freq, 0),
315+ DEFINE_PROP_CHR("chardev", RSCIState, chr),
316+ DEFINE_PROP_END_OF_LIST(),
317+};
318+
319+static void rsci_class_init(ObjectClass *klass, void *data)
320+{
321+ DeviceClass *dc = DEVICE_CLASS(klass);
322+
323+ dc->realize = rsci_realize;
324+ dc->vmsd = &vmstate_rsci;
325+ dc->reset = rsci_reset;
326+ device_class_set_props(dc, rsci_properties);
327+}
328+
329+static const TypeInfo rsci_info = {
330+ .name = TYPE_RENESAS_SCI,
331+ .parent = TYPE_SYS_BUS_DEVICE,
332+ .instance_size = sizeof(RSCIState),
333+ .instance_init = rsci_init,
334+ .class_init = rsci_class_init,
335+};
336+
337+static void rsci_register_types(void)
338+{
339+ type_register_static(&rsci_info);
340+}
341+
342+type_init(rsci_register_types)
--- /dev/null
+++ b/include/hw/char/renesas_sci.h
@@ -0,0 +1,45 @@
1+/*
2+ * Renesas Serial Communication Interface
3+ *
4+ * Copyright (c) 2018 Yoshinori Sato
5+ *
6+ * This code is licensed under the GPL version 2 or later.
7+ *
8+ */
9+
10+#include "chardev/char-fe.h"
11+#include "qemu/timer.h"
12+#include "hw/sysbus.h"
13+
14+#define TYPE_RENESAS_SCI "renesas-sci"
15+#define RSCI(obj) OBJECT_CHECK(RSCIState, (obj), TYPE_RENESAS_SCI)
16+
17+enum {
18+ ERI = 0,
19+ RXI = 1,
20+ TXI = 2,
21+ TEI = 3,
22+ SCI_NR_IRQ = 4,
23+};
24+
25+typedef struct {
26+ SysBusDevice parent_obj;
27+ MemoryRegion memory;
28+
29+ uint8_t smr;
30+ uint8_t brr;
31+ uint8_t scr;
32+ uint8_t tdr;
33+ uint8_t ssr;
34+ uint8_t rdr;
35+ uint8_t scmr;
36+ uint8_t semr;
37+
38+ uint8_t read_ssr;
39+ int64_t trtime;
40+ int64_t rx_next;
41+ QEMUTimer *timer;
42+ CharBackend chr;
43+ uint64_t input_freq;
44+ qemu_irq irq[SCI_NR_IRQ];
45+} RSCIState;