提交: 400c3c549bd998614a3b14b012010791b479799b - binutils_gdb (git)

Commit MetaInfo

• 修訂: 400c3c549bd998614a3b14b012010791b479799b (tree)
• 時間: 2018-12-23 23:29:33
• 作者: Yoshinori Sato <ysato@user...>
• Commiter: Yoshinori Sato

Log Message

add rxv3-dfpu

Change Summary

• modified: gas/config/rx-parse.y

差異

--- a/gas/config/rx-parse.y
+++ b/gas/config/rx-parse.y
@@ -120,6 +120,7 @@ static void        rtsd_immediate (expressionS);
 static void	   rx_range (expressionS, int, int);
 static void        rx_check_v2 (void);
 static void        rx_check_v3 (void);
+static void        rx_check_dfpu (void);
 
 static int    need_flag = 0;
 static int    rx_in_brackets = 0;
@@ -916,88 +917,88 @@ statement :
 	| SAVE { rx_check_v3(); sub_op = 0; } op_save_rstr
 
 /* ---------------------------------------------------------------------- */
-	| DABS { rx_check_v3(); sub_op = 0x0c; sub_op2 = 0x01; } double2_op
-	| DNEG { rx_check_v3(); sub_op = 0x0c; sub_op2 = 0x02; } double2_op
-	| DROUND { rx_check_v3(); sub_op = 0x0d; sub_op2 = 0x0d; } double2_op
-	| DSQRT { rx_check_v3(); sub_op = 0x0d; sub_op2 = 0x00; } double2_op
-	| DTOF { rx_check_v3(); sub_op = 0x0d; sub_op2 = 0x0c; } double2_op
-	| DTOI { rx_check_v3(); sub_op = 0x0d; sub_op2 = 0x08;} double2_op
-	| DTOU { rx_check_v3(); sub_op = 0x0d; sub_op2 = 0x09; } double2_op
-	| DADD { rx_check_v3(); sub_op = 0x00; } double3_op
-	| DDIV { rx_check_v3(); sub_op = 0x05; } double3_op
-	| DMUL { rx_check_v3(); sub_op = 0x02; } double3_op
-	| DSUB { rx_check_v3(); sub_op = 0x01; } double3_op
-	| DCMP DREG ',' DREG { rx_check_v3();
+	| DABS { rx_check_dfpu(); sub_op = 0x0c; sub_op2 = 0x01; } double2_op
+	| DNEG { rx_check_dfpu(); sub_op = 0x0c; sub_op2 = 0x02; } double2_op
+	| DROUND { rx_check_dfpu(); sub_op = 0x0d; sub_op2 = 0x0d; } double2_op
+	| DSQRT { rx_check_dfpu(); sub_op = 0x0d; sub_op2 = 0x00; } double2_op
+	| DTOF { rx_check_dfpu(); sub_op = 0x0d; sub_op2 = 0x0c; } double2_op
+	| DTOI { rx_check_dfpu(); sub_op = 0x0d; sub_op2 = 0x08;} double2_op
+	| DTOU { rx_check_dfpu(); sub_op = 0x0d; sub_op2 = 0x09; } double2_op
+	| DADD { rx_check_dfpu(); sub_op = 0x00; } double3_op
+	| DDIV { rx_check_dfpu(); sub_op = 0x05; } double3_op
+	| DMUL { rx_check_dfpu(); sub_op = 0x02; } double3_op
+	| DSUB { rx_check_dfpu(); sub_op = 0x01; } double3_op
+	| DCMP DREG ',' DREG { rx_check_dfpu();
 	    B4(0x76, 0x90, 0x08, 0x00); F($1, 24, 4); F($2, 28, 4); F($4, 16, 4); }
 	| DMOV DOT_D REG ',' DREGH
-	{ rx_check_v3();
+	{ rx_check_dfpu();
 	  B4(0xfd, 0x77, 0x80, 0x03); F($3, 20, 4); F($5, 24, 4); }
 	| DMOV DOT_L REG ',' DREGH
-	{ rx_check_v3();
+	{ rx_check_dfpu();
 	  B4(0xfd, 0x77, 0x80, 0x02); F($3, 20, 4); F($5, 24, 4); }
 	| DMOV DOT_L REG ',' DREGL
-	{ rx_check_v3();
+	{ rx_check_dfpu();
 	  B4(0xfd, 0x77, 0x80, 0x00); F($3, 20, 4); F($5, 24, 4); }
 	| DMOV DOT_L DREGH ',' REG
-	{ rx_check_v3();
+	{ rx_check_dfpu();
 	  B4(0xfd, 0x75, 0x80, 0x02); F($3, 24, 4); F($5, 20, 4); }
 	| DMOV DOT_L DREGL ',' REG
-	{ rx_check_v3();
+	{ rx_check_dfpu();
 	  B4(0xfd, 0x75, 0x80, 0x00); F($3, 24, 4); F($5, 20, 4); }
 	| DMOV DOT_D DREG ',' DREG
-	{ rx_check_v3();
+	{ rx_check_dfpu();
 	  B4(0x76, 0x90, 0x0c, 0x00); F($3, 16, 4); F($5, 24, 4); }
 	| DMOV DOT_D DREG ',' '[' REG ']'
-	{ rx_check_v3();
+	{ rx_check_dfpu();
 	  B4(0xfc, 0x78, 0x08, 0x00); F($6, 16, 4); F($3, 24, 4); }
 	| DMOV DOT_D DREG ',' disp '[' REG ']'
-	{ rx_check_v3();
+	{ rx_check_dfpu();
 	  B3(0xfc, 0x78, 0x08); F($7, 16, 4); DSP($5, 14, DSIZE);
 	  POST($3 << 4); }
 	| DMOV DOT_D '[' REG ']' ',' DREG
-	{ rx_check_v3();
+	{ rx_check_dfpu();
 	  B4(0xfc, 0xc8, 0x08, 0x00); F($4, 16, 4); F($7, 24, 4); }
 	| DMOV DOT_D disp '[' REG ']' ',' DREG
-	{ rx_check_v3();
+	{ rx_check_dfpu();
 	  B3(0xfc, 0xc8, 0x08); F($5, 16, 4); DSP($3, 14, DSIZE);
 	  POST($8 << 4); }
 	| DMOV DOT_D '#' EXPR ',' DREGH
-	{ rx_check_v3();
+	{ rx_check_dfpu();
 	  B3(0xf9, 0x03, 0x03); F($6, 16, 4); IMM($4, -1); }
 	| DMOV DOT_L '#' EXPR ',' DREGH
-	{ rx_check_v3();
+	{ rx_check_dfpu();
 	  B3(0xf9, 0x03, 0x02); F($6, 16, 4); IMM($4, -1); }
 	| DMOV DOT_L '#' EXPR ',' DREGL
-	{ rx_check_v3();
+	{ rx_check_dfpu();
 	  B3(0xf9, 0x03, 0x00); F($6, 16, 4); IMM($4, -1); }
 	| DPOPM DOT_D DREG '-' DREG
-	{ rx_check_v3();
+	{ rx_check_dfpu();
 	  B3(0x75, 0xb8, 0x00); F($3, 16, 4); F($5 - $3, 20, 4); }
 	| DPOPM DOT_L DCREG '-' DCREG
-	{ rx_check_v3();
+	{ rx_check_dfpu();
 	  B3(0x75, 0xa8, 0x00); F($3, 16, 4); F($5 - $3, 20, 4); }
 	| DPUSHM DOT_D DREG '-' DREG
-	{ rx_check_v3();
+	{ rx_check_dfpu();
 	  B3(0x75, 0xb0, 0x00); F($3, 16, 4); F($5 - $3, 20, 4); }
 	| DPUSHM DOT_L DCREG '-' DCREG
-	{ rx_check_v3();
+	{ rx_check_dfpu();
 	  B3(0x75, 0xa0, 0x00); F($3, 16, 4); F($5 - $3, 20, 4); }
 	| MVFDC DCREG ',' REG
-	{ rx_check_v3();
+	{ rx_check_dfpu();
 	  B4(0xfd, 0x75, 0x80, 0x04); F($2, 24, 4); F($4, 20, 4); }
 	| MVFDR
-	{ rx_check_v3(); B3(0x75, 0x90, 0x1b); }
+	{ rx_check_dfpu(); B3(0x75, 0x90, 0x1b); }
 	| MVTDC REG ',' DCREG
-	{ rx_check_v3();
+	{ rx_check_dfpu();
 	  B4(0xfd, 0x77, 0x80, 0x04); F($2, 24, 4); F($4, 20, 4); }
 	| FTOD REG ',' DREG
-	{ rx_check_v3();
+	{ rx_check_dfpu();
 	  B4(0xfd, 0x77, 0x80, 0x0a); F($2, 24, 4); F($4, 20, 4); }
 	| ITOD REG ',' DREG
-	{ rx_check_v3();
+	{ rx_check_dfpu();
 	  B4(0xfd, 0x77, 0x80, 0x09); F($2, 24, 4); F($4, 20, 4); }
 	| UTOD REG ',' DREG
-	{ rx_check_v3();
+	{ rx_check_dfpu();
 	  B4(0xfd, 0x77, 0x80, 0x0d); F($2, 24, 4); F($4, 20, 4); }
 
 /* ---------------------------------------------------------------------- */
@@ -2073,3 +2074,10 @@ rx_check_v3 (void)
   if (rx_cpu < RXV3)
     rx_error (_("target CPU type does not support v3 instructions"));
 }
+
+static void
+rx_check_dfpu (void)
+{
+  if (rx_cpu != RXV3FPU)
+    rx_error (_("target CPU type does not support double float instructions"));
+}