提交: 73ec18525884730e1e2112933923c65840a021fd - exorsim6801 (git)

Motorola M6800 (6800) Exorciser / SWTPC emulator plus 6801 instruction set emulation

Commit MetaInfo

• 修訂: 73ec18525884730e1e2112933923c65840a021fd (tree)
• 時間: 2020-11-22 02:03:25
• 作者: Joel Matthew Rees <joel.rees@gmai...>
• Commiter: Joel Matthew Rees

Log Message

buggy in 6800 mode, not sure why

Change Summary

• modified: Makefile
• modified: exor.c
• modified: exorsim.h
• modified: sim6800.c

差異

--- a/Makefile
+++ b/Makefile
@@ -1,8 +1,8 @@
 
-OBJS = unasm.o utils.o exor.o sim6800.o asm6800.o mdos.o unasm6800.o exorterm.o
+OBJS = unasm.o utils.o exor.o sim6800.o asm6800.o mdos.o unasm6800.o mon.o exorterm.o exorsim.o
 
-DIST = unasm.c utils.c exor.c sim6800.c asm6800.c mdos.c unasm6800.c mon.c exorterm.c Makefile \
-  exbug.bin swtbug.bin utils.h sim6800.h asm6800.h unasm6800.h exor.h facts README COPYING \
+DIST = unasm.c utils.c exor.c sim6800.c asm6800.c mdos.c unasm6800.c mon.c exorterm.c exorsim.c Makefile \
+  exbug.bin swtbug.bin utils.h sim6800.h asm6800.h unasm6800.h exor.h exorsim.h facts README COPYING \
   doc/doc.man doc/mdos-hello.txt doc/mdos-tech.txt doc/mdos.txt doc/mpl_upd.txt doc/mplnotes \
   doc/notes doc/fort.man
 
@@ -66,11 +66,11 @@ CC = gcc
 
 all : mdos exor unasm
 
-unasm : unasm.o utils.o unasm6800.o
-	$(CC) -o unasm unasm.o utils.o unasm6800.o
+unasm : unasm.o utils.o unasm6800.o exorsim.o
+	$(CC) -o unasm unasm.o utils.o unasm6800.o exorsim.o
 
-exor : exor.o utils.o sim6800.o asm6800.o unasm6800.o mon.o exorterm.o
-	$(CC) -o exor exor.o utils.o sim6800.o asm6800.o unasm6800.o mon.o exorterm.o
+exor : exor.o utils.o sim6800.o asm6800.o unasm6800.o mon.o exorterm.o exorsim.o
+	$(CC) -o exor exor.o utils.o sim6800.o asm6800.o unasm6800.o mon.o exorterm.o exorsim.o
 
 mdos : mdos.o
 	$(CC) -o mdos mdos.o

--- a/exor.c
+++ b/exor.c
@@ -26,6 +26,7 @@
 #include <signal.h>
 #include <unistd.h>	/* JMR20201103 */
 
+#include "exorsim.h"	/* JMR20201121 */
 #include "sim6800.h"
 #include "unasm6800.h"	/* JMR202021103 */
 #include "exor.h"
@@ -935,6 +936,8 @@ int main(int argc, char *argv[])
                                 trace = 1;
                         } else if (!strcmp(argv[x], "--swtpc")) {
                                 swtpc = 1;
+                        } else if (!strcmp(argv[x], "--6801")) {
+                                cputype = 0x6801;
                         } else if (!strcmp(argv[x], "--dtrace")) {
                                 trace_disk = 1;
                         } else if (!strcmp(argv[x], "--mon")) {
@@ -957,6 +960,7 @@ int main(int argc, char *argv[])
                                 printf("  --dtrace	Produce disk access trace on stderr\n");
                                 printf("  --skip nnn    Skip first nnn insns in trace\n");
                                 printf("  --swtpc       Simulate SWTPC instead of EXORciser\n");
+                                printf("  --6801        Simulate additional 6801 instructions\n");
                                 printf("  --exbug name	Give name for ROM if not 'exbug.bin'\n");
                                 printf("  -x            Go into EXBUG/SWTBUG instead of MDOS/FLEX\n");
                                 printf("  --facts file  Process facts files for commented disassembly\n");

--- a/exorsim.h
+++ b/exorsim.h
@@ -1,4 +1,5 @@
-/*	Configurations for Joseph H. Allen's Exorsim
+/*	Configurations include file
+ *      for modifications to Joseph H. Allen's Exorsim
  *	This file copyright 2020 Joel Matthew Rees
  *
  * This is free software; you can redistribute it and/or modify it under the 
@@ -16,7 +17,17 @@
  */
 
 
-/* #define SIM6800 0x6800 */
-#define SIM6801 0x6801
+#ifndef EXORSIM_H
+#define EXORSIM_H
 
 
+#define SIM6801 0x6800 /* Set 0x6801 by command-line flags. */
+
+
+#ifndef EXORSIM_C
+	extern unsigned cputype;
+#endif
+
+
+#endif
+

--- a/sim6800.c
+++ b/sim6800.c
@@ -157,11 +157,11 @@ unsigned short pull2()
 #define V_SUB(a,b,f) ((((a) ^ (b)) & ((f) ^ (a))) >> 7)
 #define C_SUB(a,b,f) (((~(a) & (b)) | ((~(a) | (b)) & (f))) >> 7)
 #define H(a,b,f) ((((f) ^ (a) ^ (b)) >> 4) & 1)
-#ifdef SIM6801
+/* #ifdef SIM6801 */
 #define C_16(a,b,f) ((((a) & (b)) | (((a) | (b)) & ~(f))) >> 15)
 #define V_16_SUB(a,b,f) ((((a) ^ (b)) & ((f) ^ (a))) >> 15)
 #define C_16_SUB(a,b,f) (((~(a) & (b)) | ((~(a) | (b)) & (f))) >> 15)
-#endif /* def SIM6801 */
+/* #endif / * def SIM6801 */
 
 /* Print one trace line */
 
@@ -217,11 +217,8 @@ void show_trace(int insn_no, struct trace_entry *t)
         sprintf(buf + strlen(buf), "%2.2X ", t->insn[0]);
 
 	if (t->insn[0] & 0x80) {
-#ifdef SIM6801
-		if ( ((t->insn[0] & 0x0F) < 0x0C) && ((t->insn[0] & 0x0F) != 0x03 ) ) {
-#else
-		if ((t->insn[0] & 0x0F) < 0x0C) {
-#endif /* def SIM6801 */
+		if ( ((t->insn[0] & 0x0F) < 0x0C) 
+		     && ( (cputype == 0x6801 && (t->insn[0] & 0x0F) != 0x03) ) ) {
 			if (t->insn[0] & 0x40) {
 				sprintf(operand, "B");
 			} else {
@@ -260,19 +257,13 @@ void show_trace(int insn_no, struct trace_entry *t)
 				} case 0x02: /* SBC N,Z,V,C (no H?) */ {
 					insn = "SBC";
 					break;
-				}
-#ifdef SIM6801
-				  case 0x03: /* ACCMD should never get here at run time. */ {
-					insn = "";
+				} case 0x03: /* ACCMD should never get here at run time? */ {
+					if  (cputype == 0x6800)
+						goto invalid; /* ??? */
+					else
+						insn = "SUBD***";
 					break;
-				}
-#else
-				  case 0x03: /* ??? */ {
-					goto invalid;
-					break;
-				}
-#endif /* ndef SIM6801 */
-				  case 0x04: /* AND N,Z,V=0 */ {
+				} case 0x04: /* AND N,Z,V=0 */ {
 					insn = "AND";
 					break;
 				} case 0x05: /* BIT N,Z,V=0*/ {
@@ -327,15 +318,14 @@ void show_trace(int insn_no, struct trace_entry *t)
 				}
 			}
 			switch (t->insn[0]) {
-#ifdef SIM6801
 				  case 0x83: case 0x93: case 0xA3: case 0xB3: /* SUBD N,Z,V,C (6801) */ {
+					/* Should never come here when cputype == 0x6800. */
+					/* But if it does, we want to do something defined. */
 				        if (t->cc & 0x80)
         					sprintf(buf3, "EA=%4.4X%s D=%4.4X", t->ea, buf_ea, t->data);
-					insn = "SUBD";
+					insn = (cputype == 0x6800) ? "???SUBD" : "SUBD";
 					break;
-				}
-#endif /* def SIM6801 */
-				  case 0x8C: case 0x9C: case 0xAC: case 0xBC: /* CPX N,Z,V */ {
+				} case 0x8C: case 0x9C: case 0xAC: case 0xBC: /* CPX N,Z,V */ {
 				        if (t->cc & 0x80)
         					sprintf(buf3, "EA=%4.4X%s D=%4.4X", t->ea, buf_ea, t->data);
 					insn = "CPX";
@@ -357,36 +347,36 @@ void show_trace(int insn_no, struct trace_entry *t)
         					sprintf(buf3, "EA=%4.4X%s D=%4.4X", t->ea, buf_ea, t->data);
 					insn = "STS";
 					break;
-				} 
-#ifdef SIM6801
-				  case 0x9D:	/* (6801) */
-#endif /* def SIM6801 */
-				  case 0xAD: case 0xBD: /* JSR */ {
-				        if (t->cc & 0x80)
+				} case 0x9D: case 0xAD: case 0xBD: /* JSR */ {
+					if (cputype == 0x6800 && t->insn[0] == 0x9D)
+{ fputs( "JSR\n", stderr );						goto invalid16;
+}				        else if (t->cc & 0x80)
         					sprintf(buf3, "EA=%4.4X%s", t->ea, buf_ea);
 					insn = "JSR";
 					subr = 1;
 					break;
-				}
-#ifdef SIM6801
-				  case 0xC3: case 0xD3: case 0xE3: case 0xF3: /* ADDD N,Z,V,C (6801) */ {
-				        if (t->cc & 0x80)
+				} case 0xC3: case 0xD3: case 0xE3: case 0xF3: /* ADDD N,Z,V,C (6801) */ {
+					if (cputype == 0x6800)
+{ fputs( "ADDD\n", stderr );						goto invalid16;
+}				        else if (t->cc & 0x80)
         					sprintf(buf3, "EA=%4.4X%s D=%4.4X", t->ea, buf_ea, t->data);
 					insn = "ADDD";
 					break;
 				} case 0xCC: case 0xDC: case 0xEC: case 0xFC: /* LDD N,Z,V=0 (6801) */ {
-				        if (t->cc & 0x80)
+				        if (cputype == 0x6800)
+{ fputs( "LDD\n", stderr );						goto invalid16;
+}				        else if (t->cc & 0x80)
         					sprintf(buf3, "EA=%4.4X%s D=%4.4X", t->ea, buf_ea, t->data);
 					insn = "LDD";
 					break;
 				} case 0xCD: case 0xDD: case 0xED: case 0xFD: /* STD N,Z,V=0 (6801) */ {
-				        if (t->cc & 0x80)
+				        if (cputype == 0x6800)
+{ fputs( "STD\n", stderr );						goto invalid16;
+}				        else if (t->cc & 0x80)
         					sprintf(buf3, "EA=%4.4X%s D=%4.4X", t->ea, buf_ea, t->data);
 					insn = "STD";
 					break;
-				}
-#endif /* def SIM6801 */
-				  case 0xCE: case 0xDE: case 0xEE: case 0xFE: /* LDX N,Z,V */ {
+				} case 0xCE: case 0xDE: case 0xEE: case 0xFE: /* LDX N,Z,V */ {
 				        if (t->cc & 0x80)
         					sprintf(buf3, "EA=%4.4X%s D=%4.4X", t->ea, buf_ea, t->data);
 					insn = "LDX";
@@ -397,6 +387,8 @@ void show_trace(int insn_no, struct trace_entry *t)
 					insn = "STX";
 					break;
 				} default: /* ??? */ {
+invalid16:
+fprintf( stderr, "invalid16 from mnemonic: %x\n", t->insn[0] );
 					goto invalid;
 					break;
 				}
@@ -481,17 +473,19 @@ void show_trace(int insn_no, struct trace_entry *t)
 			case 0x01: /* NOP */ { /* Do nothing */
 				insn = "NOP";
 				break;
-			}
-#ifdef SIM6801
- 			  case 0x04: /* LSRD N=0,Z,V,C (6801) */ {
-				insn = "LSRD";
+			} case 0x04: /* LSRD N=0,Z,V,C (6801) */ {
+				if (cputype == 0x6800)
+					goto invalidinh;
+				else
+					insn = "LSRD";
 				break;
 			} case 0x05: /* LSLD N,Z,V,C (6801) */ {
-				insn = "LSLD";
+				if (cputype == 0x6800)
+					goto invalidinh;
+				else
+					insn = "LSLD";
 				break;
-			}
-#endif /* def SIM6801 */
-			  case 0x06: /* TAP (all flags) */ {
+			} case 0x06: /* TAP (all flags) */ {
 				insn = "TAP";
 				break;
 			} case 0x07: /* TPA */ {
@@ -546,18 +540,18 @@ void show_trace(int insn_no, struct trace_entry *t)
                                         sprintf(buf3, "EA=%4.4X%s", t->ea, buf_ea);
 				insn = "BRA";
 				break;
-			}
-#ifdef SIM6801
-			  case 0x21: /* BRN (6801) */ {
-				sprintf(buf + strlen(buf), "%2.2X ", t->insn[1]);
-				sprintf(operand, " %4.4X", t->pc + 2 + (char)t->insn[1]);
-                                if (t->cc & 0x80)
-                                        sprintf(buf3, "EA=%4.4X%s", t->ea, buf_ea);
-				insn = "BRN";
+			} case 0x21: /* BRN (6801) */ {
+				if (cputype == 0x6800)
+					goto invalidinh;
+				else {
+					sprintf(buf + strlen(buf), "%2.2X ", t->insn[1]);
+					sprintf(operand, " %4.4X", t->pc + 2 + (char)t->insn[1]);
+                                	if (t->cc & 0x80)
+                                        	sprintf(buf3, "EA=%4.4X%s", t->ea, buf_ea);
+					insn = "BRN";
+				}
 				break;
-			}
-#endif /* def SIM6801 */
-			  case 0x22: /* BHI */ {
+			} case 0x22: /* BHI */ {
 				sprintf(buf + strlen(buf), "%2.2X ", t->insn[1]);
 				sprintf(operand, " %4.4X", t->pc + 2 + (char)t->insn[1]);
                                 if (t->cc & 0x80)
@@ -679,45 +673,46 @@ void show_trace(int insn_no, struct trace_entry *t)
 			} case 0x37: /* PSHB */ {
 				insn = "PSHB";
 				break;
-			}
-#ifdef SIM6801
-			  case 0x38: /* PULX (6801) */ {
-				insn = "PULX";
+			} case 0x38: /* PULX (6801) */ {
+				if (cputype == 0x6800)
+					goto invalidinh;
+				else
+					insn = "PULX";
 				break;
-			}
-#endif /* def SIM6801 */
-			  case 0x39: /* RTS */ {
+			} case 0x39: /* RTS */ {
 				insn = "RTS";
 				subr = 1;
 				break;
-			}
-#ifdef SIM6801
- 			  case 0x3A: /* ABX (6801) */ {
-				insn = "ABX";
+			} case 0x3A: /* ABX (6801) */ {
+				if (cputype == 0x6800)
+					goto invalidinh;
+				else
+					insn = "ABX";
 				break;
-			}
-#endif /* def SIM6801 */
-			  case 0x3B: /* RTI */ {
+			} case 0x3B: /* RTI */ {
 				insn = "RTI";
 				subr = 1;
 				break;
-			}
-#ifdef SIM6801
-			  case 0x3C: /* PSHX (6801) */ {
-				insn = "PSHX";
+			} case 0x3C: /* PSHX (6801) */ {
+				if (cputype == 0x6800)
+					goto invalidinh;
+				else
+					insn = "PSHX";
 				break;
 			} case 0x3D: /* MUL C=accb bit 7 (6801) */ {
-				insn = "MUL";
+				if (cputype == 0x6800)
+					goto invalidinh;
+				else
+					insn = "MUL";
 				break;
-			}
-#endif /* def SIM6801 */
-			  case 0x3E: /* WAI */ {
+			} case 0x3E: /* WAI */ {
 				insn = "WAI";
 				break;
 			} case 0x3F: /* SWI */ {
 				insn = "SWI";
 				break;
 			} default: /* ??? */ {
+invalidinh:
 				goto invalid;
 				break;
 			}
@@ -775,11 +770,9 @@ void sim(void)
 		unsigned char b;
 		unsigned char f;
 		unsigned char data;
-#ifdef SIM6801
 		unsigned short accd;
 #define setACCD( val ) ( val = ( ( (unsigned int) acca ) << 8 ) | ( (unsigned char) accb ) )
 #define restoreACCM( res ) ( acca = (unsigned char) ( (res) >> 8 ), accb = ( (unsigned char) (res) ) )
-#endif /* def SIM6801 */
 		unsigned short w;
 		unsigned short fw;
 		int wb;
@@ -859,11 +852,8 @@ void sim(void)
 		opcode = fetch();
 
 		if (opcode & 0x80) {
-#ifdef SIM6801
-			if ( ((opcode & 0x0F) < 0x0C) && ((opcode & 0x0F) != 0x03) ) {
-#else
-			if ((opcode & 0x0F) < 0x0C) {
-#endif /* def SIM6801 */
+			if ( ((opcode & 0x0F) < 0x0C)  
+			     && (cputype == 0x6801 && ((opcode & 0x0F) != 0x03)) ) {
 				/* Get operand A */
 				if (opcode & 0x40) {
 					a = accb;
@@ -919,14 +909,12 @@ void sim(void)
 						n_flag = N(f);
 						z_flag = Z(f);
 						break;
-					}
-#ifndef SIM6801
-					  case 0x03: /* ??? */ {
+					} case 0x03: /* ??? */ {
+						if  (cputype == 0x6801)
+							fprintf( stderr, "Internal error on SUBD (6801)\n" );
 					        goto invalid;
 					        break;
-					}
-#endif /* ndef SIM6801 */
-					  case 0x04: /* AND N,Z,V=0 */ {
+					} case 0x04: /* AND N,Z,V=0 */ {
 						f = (a & b);
 						n_flag = N(f);
 						z_flag = Z(f);
@@ -1006,35 +994,36 @@ void sim(void)
 					}
 				}
 				switch (opcode) {
-#ifdef SIM6801
 					  case 0x83: case 0x93: case 0xA3: case 0xB3: /* SUBD N,Z,V,C (6801) */ {
-						setACCD( accd );
-						w = mread2(ea);
-                                                t->ea = ea; t->data = w;
-						fw = accd - w;
-						z_flag = Z_16(fw);
-						n_flag = N_16(fw);
-						v_flag = V_16_SUB(accd, w, fw);
-						c_flag = C_16_SUB(accd, w, fw);
-						restoreACCM( fw );
+						if (cputype == 0x6800) {
+							fprintf( stderr, "Internal error on SUBD (6800)\n" );
+							goto invalid16;
+						}
+						else {
+							setACCD( accd );
+							w = mread2(ea);
+	                                                t->ea = ea; t->data = w;
+							fw = accd - w;
+							z_flag = Z_16(fw);
+							n_flag = N_16(fw);
+							v_flag = V_16_SUB(accd, w, fw);
+							c_flag = C_16_SUB(accd, w, fw);
+							restoreACCM( fw );
+						}
 						break;
-					}
-#endif /* def SIM6801 */
-					  case 0x8C: case 0x9C: case 0xAC: case 0xBC: /* CPX (N_hi8),Z,(V_hi8) JMR20201103 */ {
+					} case 0x8C: case 0x9C: case 0xAC: case 0xBC: /* CPX (N_hi8),Z,(V_hi8) JMR20201103 */ {
 						w = mread2(ea);
                                                 t->ea = ea; t->data = w;
 						fw = ix - w;
 						z_flag = Z_16(fw);
-#if defined SIM6801
-						n_flag = N_16(fw);
-						v_flag = V_16(ix, w, fw);
-#elif defined SIM6800
-						f = ( ix >> 8 ) - ( w >> 8 );
-						n_flag = N(f);
-						v_flag = V(ix >> 8, w >> 8, f);
-#else
-#	error "68HC11, etc. not defined here!"
-#endif /* defined SIM6800 */
+						if (cputype == 0x6800) {
+							f = ( ix >> 8 ) - ( w >> 8 );
+							n_flag = N(f);
+							v_flag = V(ix >> 8, w >> 8, f);
+						} else { /* assume 0x6801 compatible for now. */
+							n_flag = N_16(fw);
+							v_flag = V_16(ix, w, fw);
+						}
 						break;
 					} case 0x8D: /* BSR REL */ {
 						push2(pc - 1);
@@ -1055,46 +1044,56 @@ void sim(void)
 						v_flag = 0;
 						break;
 					}
-#ifdef SIM6801
 					  case 0x9D:	/* (6801) */
-#endif /* def SIM6801 */
 					  case 0xAD: case 0xBD: /* JSR */ {
-						push2(pc);
-						jump(ea);
-                                                t->ea = ea;
+						if (cputype == 0x6800 && opcode == 0x9D)
+							goto invalid16;
+						else {
+							push2(pc);
+							jump(ea);
+        	                                        t->ea = ea;
+						}
 						break;
-					}
-#ifdef SIM6801
-					  case 0xC3: case 0xD3: case 0xE3: case 0xF3: /* ADDD N,Z,V,C (6801) */ {
-						setACCD( accd );
-						w = mread2(ea);
-						t->ea = ea; t->data = w;
-						fw = accd + w;
-						z_flag = Z_16(fw);
-						n_flag = N_16(fw);
-						v_flag = V_16(accd, w, fw);
-						c_flag = C_16(accd, w, fw);
-						restoreACCM( fw );
+					} case 0xC3: case 0xD3: case 0xE3: case 0xF3: /* ADDD N,Z,V,C (6801) */ {
+						if (cputype == 0x6800)
+							goto invalid16;
+						else {
+							setACCD( accd );
+							w = mread2(ea);
+							t->ea = ea; t->data = w;
+							fw = accd + w;
+							z_flag = Z_16(fw);
+							n_flag = N_16(fw);
+							v_flag = V_16(accd, w, fw);
+							c_flag = C_16(accd, w, fw);
+							restoreACCM( fw );
+						}
 						break;
 					} case 0xCC: case 0xDC: case 0xEC: case 0xFC: /* LDD N,Z,V=0 (6801) */ {
-						accd = mread2(ea);
-                                                t->ea = ea; t->data = accd;
-						z_flag = Z_16( accd );
-						n_flag = N_16( accd );
-						v_flag = 0;
-						restoreACCM( accd );
+						if (cputype == 0x6800)
+							goto invalid16;
+						else {
+							accd = mread2(ea);
+		                                        t->ea = ea; t->data = accd;
+							z_flag = Z_16( accd );
+							n_flag = N_16( accd );
+							v_flag = 0;
+							restoreACCM( accd );
+						}
 						break;
 					} case 0xDD: case 0xED: case 0xFD: /* STD N,Z,V=0 (6801) */ {
-						setACCD( accd );
-						n_flag = N_16( accd );
-						z_flag = Z_16( accd );
-					        v_flag = 0;
-						mwrite2( ea, accd );
-                                                t->ea = ea; t->data = accd;
+						if (cputype == 0x6800)
+							goto invalid16;
+						else {
+							setACCD( accd );
+							n_flag = N_16( accd );
+							z_flag = Z_16( accd );
+							v_flag = 0;
+							mwrite2( ea, accd );
+		                                        t->ea = ea; t->data = accd;
+						}
 						break;
-					}
-#endif /* def SIM6801 */
-					  case 0xCE: case 0xDE: case 0xEE: case 0xFE: /* LDX N,Z,V */ {
+					} case 0xCE: case 0xDE: case 0xEE: case 0xFE: /* LDX N,Z,V */ {
 						ix = mread2(ea);
                                                 t->ea = ea; t->data = ix;
 						z_flag = Z_16(ix);
@@ -1109,6 +1108,9 @@ void sim(void)
 						v_flag = 0;
 						break;
 					} default: /* ??? */ {
+invalid16:
+fprintf( stderr, "invalid16 from opcode: %x => %x\n", t->insn[0], opcode );
+
 					        goto invalid;
 						break;
 					}
@@ -1250,31 +1252,35 @@ void sim(void)
                 	switch(opcode) {
 				case 0x01: /* NOP */ { /* Do nothing */
 					break;
-				}
-#ifdef SIM6801
-				  case 0x04: /* LSRD (6801) */ {
-					setACCD( accd );
-					t->data = accd;
-					fw = (accd >> 1);
-					c_flag = (accd & 1);
-					n_flag = 0;
-					z_flag = Z_16(fw);
-					v_flag = n_flag ^ c_flag;
-					restoreACCM( fw );
+				} case 0x04: /* LSRD (6801) */ {
+					if (cputype == 0x6800)
+						goto invalidinh;
+					else {
+						setACCD( accd );
+						t->data = accd;
+						fw = (accd >> 1);
+						c_flag = (accd & 1);
+						n_flag = 0;
+						z_flag = Z_16(fw);
+						v_flag = n_flag ^ c_flag;
+						restoreACCM( fw );
+					}
 					break;
 				} case 0x05: /* LSLD (6801) */ {
-					setACCD( accd );
-					t->data = accd;
-					fw = (accd << 1);
-					c_flag = (accd >> 15);
-					n_flag = N_16(fw);
-					z_flag = Z_16(fw);
-					v_flag = n_flag ^ c_flag;
-					restoreACCM( fw );
+					if (cputype == 0x6800)
+						goto invalidinh;
+					else {
+						setACCD( accd );
+						t->data = accd;
+						fw = (accd << 1);
+						c_flag = (accd >> 15);
+						n_flag = N_16(fw);
+						z_flag = Z_16(fw);
+						v_flag = n_flag ^ c_flag;
+						restoreACCM( fw );
+					}
 					break;
-				}
-#endif /* def SIM6801 */
-				  case 0x06: /* TAP (all flags) */ {
+				} case 0x06: /* TAP (all flags) */ {
 					write_flags(acca);
 					break;
 				} case 0x07: /* TPA */ {
@@ -1360,15 +1366,15 @@ void sim(void)
 					offset = fetch();
 					jump(t->ea = (pc + offset));
 					break;
-				}
-#ifdef SIM6801
-				  case 0x21: /* BRN (6801) */ {
-					offset = fetch();
-					t->ea = pc + offset;
+				} case 0x21: /* BRN (6801) */ {
+					if (cputype == 0x6800)
+						goto invalidinh;
+					else {
+						offset = fetch();
+						t->ea = pc + offset;
+					}
 					break;
-				}
-#endif /* def SIM6801 */
-				  case 0x22: /* BHI */ {
+				} case 0x22: /* BHI */ {
 					offset = fetch();
 					t->ea = pc + offset;
 					if (!(c_flag | z_flag))
@@ -1476,48 +1482,52 @@ void sim(void)
 				} case 0x37: /* PSHB */ {
 					push(accb);
 					break;
-				}
-#ifdef SIM6801
-				  case 0x38: /* PULX (6801) */ {
-					ix = pull2();
+				} case 0x38: /* PULX (6801) */ {
+					if (cputype == 0x6800)
+						goto invalidinh;
+					else {
+						ix = pull2();
+					}
 					break;
-				}
-#endif /* def SIM6801 */
-				  case 0x39: /* RTS */ {
+				} case 0x39: /* RTS */ {
 				        if (sp == sp_stop) {
 				                stop = 1;
 				                sp_stop = -1;
 				        } else
         					jump(pull2());
 					break;
-				}
-#ifdef SIM6801
-				  case 0x3A: /* ABX (6801) */ {
-					ix = ix + accb;
+				} case 0x3A: /* ABX (6801) */ {
+					if (cputype == 0x6800)
+						goto invalidinh;
+					else {
+						ix = ix + accb;
+					}
 					break;
-				}
-#endif /* def SIM6801 */
-				  case 0x3B: /* RTI */ {
+				} case 0x3B: /* RTI */ {
 					write_flags(pull());
 					accb = pull();
 					acca = pull();
 					ix = pull2();
 					jump(pull2());
 					break;
-				}
-#ifdef SIM6801
-				  case 0x3C: /* PSHX (6801) */ {
-					push2(ix);
+				} case 0x3C: /* PSHX (6801) */ {
+					if (cputype == 0x6800)
+						goto invalidinh;
+					else {
+						push2(ix);
+					}
 					break;
 				} case 0x3D: /* MUL C=accb bit 7 (6801) */ {
-					unsigned product = acca * accb;
-					accb = (unsigned char) product;
-					acca = (unsigned char) ( product >> 8 );
-					c_flag = N(acca);
+					if (cputype == 0x6800)
+						goto invalidinh;
+					else {
+						unsigned product = acca * accb;
+						accb = (unsigned char) product;
+						acca = (unsigned char) ( product >> 8 );
+						c_flag = N(acca);
+					}
 					break;
-				}
-#endif /* def SIM6801 */
-				  case 0x3E: /* WAI */ {
+				} case 0x3E: /* WAI */ {
 				        printf("WAI encountered...\n");
 				        return;
 					break;
@@ -1530,6 +1540,7 @@ void sim(void)
 					jump(mread2(0xFFFA));
 					break;
 				} default: /* ??? */ {
+invalidinh:
 				        goto invalid;
 					break;
 				}