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修訂f0331a1b39bd90d4061a949da84e68d9763f5c06 (tree)
時間2020-09-17 10:58:40
作者Satoshi Yasuda <7m3tjz@jarl...>
CommiterSatoshi Yasuda

Log Message

modified: Makefile.am
modified: dmonitor.h
modified: dmonitor_utils.c
modified: dvap.c
modified: dvap.h
modified: dvap_utils.c
new file: dvmega.c
new file: dvmega_conf.c
new file: dvmega_utils.c
modified: main.c
modified: rig_read.c
modified: rpt_conn.h

Change Summary

差異

--- a/Makefile.am
+++ b/Makefile.am
@@ -1,5 +1,5 @@
11 bin_PROGRAMS = dmonitor repeater_mon repeater_mon_light repeater_scan rpt_conn rig_check
2-dmonitor_SOURCES = main.c dmonitor_utils.c init.c inet_read.c rig_read.c dvap_utils.c dvap.c dvap_conf.c dstar_data.c crc.c send_msg.c crc.h dvap.h dmonitor.h init.h config.h dstar.h
2+dmonitor_SOURCES = main.c dmonitor_utils.c init.c inet_read.c rig_read.c dvap_utils.c dvap.c dvap_conf.c dvmega.c dvmega_conf.c dstar_data.c crc.c send_msg.c dvmega_utils.c crc.h dvap.h dmonitor.h init.h config.h dstar.h
33 dmonitor_LDADD = -lwiringPi -lcrypto
44 repeater_mon_SOURCES = repeater_mon.c repeater_mon.h
55 repeater_mon_light_SOURCES = repeater_mon_light.c repeater_mon.h
--- a/dmonitor.h
+++ b/dmonitor.h
@@ -56,6 +56,7 @@
5656 #define SHORT_TEMP "/var/tmp/short_msg.tmp"
5757 #define BUFF_HOLD "/var/www/buff_hold.txt"
5858 #define DVAP_CONF "/var/www/dvap.conf"
59+#define DVMEGA_CONF "/var/www/dvmega.conf"
5960 #define RIG_DEVICE "/dev/dstar"
6061 #define RIG_FILE "/var/www/rig.type"
6162 #define IDxxPlus_SPEED B38400
@@ -227,3 +228,19 @@ int code_sq;
227228 unsigned char msg_temp[21];
228229 unsigned char mycall2[4];
229230 char send_msg_sw;
231+
232+unsigned char rig_buff[1024];
233+
234+/* DVMEGA */
235+unsigned int m_rxFrequency;
236+unsigned int m_txFrequency;
237+unsigned int m_power;
238+int m_rxDCOffset;
239+int m_txDCOffset;
240+float m_rxLevel;
241+
242+long int dvmega_rx_freq;
243+long int dvmega_tx_freq;
244+long int dvmega_freq;
245+
246+
--- a/dmonitor_utils.c
+++ b/dmonitor_utils.c
@@ -62,6 +62,7 @@ int rig_open(void)
6262
6363 if (!scan_sw) syslog (LOG_INFO, "RIG open");
6464 else fprintf (status_fd, "RIG open.\n");
65+ rig_buff_pnt = 0;
6566 FD_SET (rig_fd, &fd_save);
6667 return TRUE;
6768 }
--- a/dvap.c
+++ b/dvap.c
@@ -293,6 +293,7 @@ void dvap(void)
293293 dvap_loop_cnt = 0;
294294 dvap_state = DVAP_TX_FREQUENCY_WAIT;
295295 break;
296+
296297 case DVAP_TX_FREQUENCY_WAIT:
297298 if (!dvap_check_wait)
298299 {
--- a/dvap.h
+++ b/dvap.h
@@ -95,7 +95,7 @@ int dvap_sw;
9595 long int dvap_freq;
9696 long int dvap_rx_freq;
9797 long int dvap_tx_freq;
98-signed char dvap_squelch;
98+unsigned char dvap_squelch;
9999 short int dvap_calibration;
100100 int dvap_auto_calibration;
101101 int dvap_auto_calibration_set;
--- a/dvap_utils.c
+++ b/dvap_utils.c
@@ -16,42 +16,6 @@ int dvap_loop_cnt;
1616 int band_scan_sw;
1717 char rssi[201];
1818
19-#if 0
20-int dvap_open(void)
21-{
22- struct termios attr;
23- int ret;
24-
25- if (rig_fd <= 0)
26- {
27- rig_fd = open(RIG_DEVICE, O_RDWR | O_NOCTTY | O_NONBLOCK | O_SYNC);
28- if (rig_fd < 0)
29- {
30- syslog (LOG_ERR, "dvap open error ");
31- return FALSE;
32- }
33- tcgetattr(rig_fd, &attr);
34- save_attr = attr;
35- }
36- bzero (&attr, sizeof(attr));
37- FD_SET (rig_fd, &fd_save);
38- cfsetispeed(&attr, DVAP_SPEED);
39- cfsetospeed(&attr, DVAP_SPEED);
40- cfmakeraw(&attr);
41- attr.c_cflag |= CS8 | CLOCAL | CSTOPB | CREAD;
42- attr.c_iflag = IGNPAR;
43- attr.c_oflag = 0;
44- attr.c_lflag = 0;
45- attr.c_cc[VMIN] = 0;
46- attr.c_cc[VTIME] = 0;
47- tcsetattr(rig_fd, TCSANOW, &attr);
48- ioctl(rig_fd, TCSETS, &attr);
49-
50- syslog (LOG_INFO, "DVAP open.");
51- return TRUE;
52-}
53-#endif
54-
5519 void dvap_init (void)
5620 {
5721 ssize_t len;
--- /dev/null
+++ b/dvmega.c
@@ -0,0 +1,284 @@
1+#include "dmonitor.h"
2+#include "dstar.h"
3+#include "dvmega.h"
4+
5+int dvmega_setMode(unsigned char mode);
6+void dvmega_close (void);
7+int dvmega_setFrequency(void);
8+int send_dvmega_status(void);
9+
10+void dvap_voice_send (char voice[]);
11+void dvap_header_send (char header[]);
12+void dvap_skip(void);
13+void dvap_send_wait_set(void);
14+int inet_send_buff_set(void);
15+void inet_led_onoff(void);
16+void dstar_data(unsigned char string[], int inet);
17+void short_msg_wrt (void);
18+void send_msg (unsigned char str[], unsigned char my2[]);
19+
20+struct termios save_attr;
21+char dvap_buff[1024];
22+char dvap_header[47];
23+char dvap_voice[18];
24+char dvmega_check_status;
25+char rssi[201];
26+
27+extern char RunState[];
28+
29+extern char error_check[];
30+
31+
32+enum
33+{
34+ DVMEGA_IDLE = 0,
35+ DVMEGA_ERROR_CHECK,
36+ DVMEGA_ERROR_CHECK_WAIT,
37+ DVMEGA_MODULATION,
38+ DVMEGA_MODULATION_CHECK,
39+ DVMEGA_MODULATION_WAIT,
40+ DVMEGA_FREQUENCY,
41+ DVMEGA_FREQUENCY_CHECK,
42+ DVMEGA_FREQUENCY_WAIT,
43+ DVMEGA_SQUELCH,
44+ DVMEGA_SQUELCH_CHECK,
45+ DVMEGA_SQUELCH_WAIT,
46+ DVMEGA_RUN,
47+} dvmega_state = DVMEGA_ERROR_CHECK;
48+
49+
50+void dvmega_last_frame_send (void)
51+{
52+ if (!dvmega_voice_send_sw) return;
53+ dvmega_last_frame_sw = FALSE;
54+}
55+
56+void dvmega(void)
57+{
58+ int ret;
59+ int offset_tmp;
60+ long int freq;
61+ int k;
62+ int step;
63+ ssize_t len;
64+
65+ signed char squelch[5] = {0x05, 0x00, 0x80, 0x00, 0x00};
66+
67+ struct timeval timer_tmp1;
68+ struct timeval timer_tmp2;
69+ time_t cur_time;
70+
71+ gettimeofday (&timer_tmp2, NULL);
72+ timersub (&timer_tmp2, &dvmega_status_send, &timer_tmp1);
73+ timer_tmp2.tv_sec = 0;
74+ timer_tmp2.tv_usec = 250000;
75+ if (timercmp (&timer_tmp1, &timer_tmp2, >))
76+ {
77+ send_dvmega_status();
78+ }
79+
80+ switch (dvmega_state)
81+ {
82+ case DVMEGA_IDLE:
83+ if (dvmega_last_frame_sw)
84+ {
85+ gettimeofday (&timer_tmp2, NULL);
86+ timersub (&timer_tmp2, &dvmega_InTime, &timer_tmp1);
87+ timer_tmp2.tv_sec = 0;
88+ timer_tmp2.tv_usec = 500000;
89+ if (timercmp (&timer_tmp1, &timer_tmp2, >))
90+ {
91+ dvmega_last_frame_send();
92+ }
93+ }
94+ break;
95+
96+ case DVMEGA_ERROR_CHECK:
97+ dvmega_check_wait = FALSE;
98+ len = write (rig_fd, error_check, 4);
99+ if (len < 0)
100+ {
101+ dvmega_close();
102+ return;
103+ }
104+ dvmega_loop_cnt = 0;
105+ dvmega_state = DVMEGA_ERROR_CHECK_WAIT;
106+ break;
107+
108+ case DVMEGA_ERROR_CHECK_WAIT:
109+ if (!dvmega_check_wait)
110+ {
111+ if (dvmega_loop_cnt++ > 50)
112+ {
113+ dvmega_state = DVMEGA_ERROR_CHECK;
114+ }
115+ break;
116+ }
117+ if (dvmega_check_status != 0x00)
118+ dvmega_state = DVMEGA_ERROR_CHECK;
119+ else
120+ dvmega_state = DVMEGA_MODULATION;
121+ break;
122+
123+ case DVMEGA_MODULATION:
124+ if (dvmega_setMode(MODE_DSTAR) != 4)
125+ {
126+ dvmega_close ();
127+ return;
128+ }
129+ dvmega_state = DVMEGA_MODULATION_CHECK;
130+ break;
131+
132+ case DVMEGA_MODULATION_CHECK:
133+ dvmega_check_wait = FALSE;
134+ len = write (rig_fd, error_check, 4);
135+
136+ if (len < 0)
137+ {
138+ dvmega_close();
139+ return;
140+ }
141+ dvmega_loop_cnt = 0;
142+ dvmega_state = DVMEGA_MODULATION_WAIT;
143+ break;
144+
145+ case DVMEGA_MODULATION_WAIT:
146+ if (!dvmega_check_wait)
147+ {
148+ if (dvmega_loop_cnt++ > 50)
149+ {
150+ dvmega_state = DVMEGA_MODULATION;
151+ }
152+ break;
153+ }
154+ if (dvmega_check_status == 0x01)
155+ {
156+ dvmega_state = DVMEGA_MODULATION_CHECK;
157+ }
158+ else if (dvmega_check_status != 0x00)
159+ {
160+ dvmega_state = DVMEGA_MODULATION;
161+ }
162+ else
163+ {
164+ dvmega_state = DVMEGA_FREQUENCY;
165+ time(&cur_time);
166+ syslog (LOG_INFO, "DVMEGA D-STAR Modulation set\n");
167+ }
168+ break;
169+
170+ case DVMEGA_FREQUENCY:
171+ if (dvmega_setFrequency())
172+ {
173+ dvmega_state = DVMEGA_FREQUENCY_CHECK;
174+ }
175+ else
176+ {
177+ time(&cur_time);
178+ syslog (LOG_ERR, "DVMEGA write (freuqncy) error %s\n",
179+ strerror(errno));
180+ dvmega_close();
181+ return;
182+ }
183+ break;
184+
185+ case DVMEGA_FREQUENCY_CHECK:
186+ dvmega_check_wait = FALSE;
187+ len = write (rig_fd, error_check, 4);
188+
189+ if (len < len)
190+ {
191+ dvmega_close();
192+ return;
193+ }
194+ dvmega_loop_cnt = 0;
195+ dvmega_state = DVMEGA_FREQUENCY_WAIT;
196+ break;
197+
198+ case DVMEGA_FREQUENCY_WAIT:
199+ if (!dvmega_check_wait)
200+ {
201+ if (dvmega_loop_cnt++ > 50)
202+ {
203+ dvmega_state = DVMEGA_FREQUENCY;
204+ }
205+ break;
206+ }
207+ if (dvmega_check_status == 0x01)
208+ {
209+ dvmega_state = DVMEGA_FREQUENCY_CHECK;
210+ }
211+ else if (dvmega_check_status != 0x00)
212+ {
213+ dvmega_state = DVMEGA_FREQUENCY;
214+ }
215+ else
216+ {
217+ dvmega_state = DVMEGA_SQUELCH;
218+ time(&cur_time);
219+ syslog (LOG_INFO, "DVMEGA TX/RX Frequency Set %ld Hz",
220+ dvmega_freq);
221+ }
222+ break;
223+
224+ case DVMEGA_SQUELCH:
225+ if (dvmega_squelch)
226+ {
227+ squelch[4] = dvmega_squelch;
228+ len = write (rig_fd, squelch, 5);
229+ dvmega_state = DVMEGA_SQUELCH_CHECK;
230+ }
231+ else
232+ dvmega_state = DVMEGA_RUN;
233+ break;
234+
235+ case DVMEGA_SQUELCH_CHECK:
236+ dvmega_check_wait = FALSE;
237+ len = write (rig_fd, error_check, 4);
238+ if (len < 0)
239+ {
240+ dvmega_close();
241+ return;
242+ }
243+ dvmega_loop_cnt = 0;
244+ dvmega_state = DVMEGA_SQUELCH_WAIT;
245+ break;
246+
247+ case DVMEGA_SQUELCH_WAIT:
248+ if (!dvmega_check_wait)
249+ {
250+ if (dvmega_loop_cnt++ > 50)
251+ {
252+ dvmega_state = DVMEGA_SQUELCH;
253+ }
254+ break;
255+ }
256+ if (dvmega_check_status == 0x01)
257+ {
258+ dvmega_state = DVMEGA_SQUELCH_CHECK;
259+ }
260+ else if (dvmega_check_status != 0x00)
261+ {
262+ dvmega_state = DVMEGA_SQUELCH;
263+ }
264+ else
265+ {
266+ dvmega_state = DVMEGA_RUN;
267+ syslog (LOG_INFO, "DVMEGA Squelch Set %d",
268+ dvmega_squelch);
269+ }
270+ break;
271+
272+ case DVMEGA_RUN:
273+ RunState[4] = 0x01;
274+ len = write (rig_fd, RunState, 5);
275+ if (len < 0)
276+ {
277+ dvmega_close ();
278+ return;
279+ }
280+ dvmega_state = DVMEGA_IDLE;
281+ break;
282+ }
283+}
284+
--- /dev/null
+++ b/dvmega_conf.c
@@ -0,0 +1,78 @@
1+#include "dmonitor.h"
2+#include "dstar.h"
3+#include "dvap.h"
4+
5+
6+void dvmega_conf (void)
7+{
8+ char buff[256];
9+ char *delmi = "=\n\r\t\0";
10+ char *pnt;
11+ char *p;
12+ int n;
13+ int field_sw;
14+ int port;
15+
16+ FILE *config_file;
17+
18+ config_file = fopen (DVMEGA_CONF, "r");
19+ if (!config_file)
20+ {
21+ syslog (LOG_ERR, "dvmega config file not found (%s)\n",
22+ DVMEGA_CONF);
23+ return;
24+ }
25+
26+ while (fgets (buff, 255, config_file))
27+ {
28+ if (buff[0] != '#')
29+ {
30+ n = 0;
31+ while (buff[n] == 0x20) n++;
32+ p = strtok(&buff[n], delmi);
33+ if (p != NULL)
34+ {
35+ pnt = strtok(NULL, delmi);
36+
37+ if (!memcmp (p, "DVMEGA_TX_FREQUENCY", 19))
38+ {
39+ dvmega_tx_freq = atoi(pnt);
40+ }
41+ else if (!memcmp (p, "DVMEGA_RX_FREQUENCY", 19))
42+ {
43+ dvmega_rx_freq = atoi (pnt);
44+ }
45+ else if (!memcmp (p, "DVMEGA_FREQUENCY", 16))
46+ {
47+ dvmega_freq = atoi (pnt);
48+ }
49+#if 0
50+ else if (!memcmp (p, "DVMEGA_SQUELCH", 14))
51+ {
52+ dvmega_squelch = atoi (pnt);
53+ if ((dvap_squelch > -45) || (dvap_squelch < -128)) dvap_squelch = 0;
54+ }
55+ else if (!memcmp (p, "DVAP_CALIBRATION", 16))
56+ {
57+ dvap_calibration = atoi (pnt);
58+ if ((dvap_calibration < -2000) || (dvap_calibration > 2000)) dvap_calibration = 0;
59+ }
60+ else if (!memcmp (p, "DVAP_AUTO_CALIBRATION", 21))
61+ {
62+ dvap_auto_calibration = atoi (pnt);
63+ }
64+#endif
65+ else
66+ {
67+ syslog (LOG_ERR, "Error on dvmega config file : %s", buff);
68+ }
69+ }
70+ }
71+ }
72+
73+ fclose (config_file);
74+
75+ return;
76+}
77+
78+
--- /dev/null
+++ b/dvmega_utils.c
@@ -0,0 +1,208 @@
1+#include "dmonitor.h"
2+#include "dvmega.h"
3+
4+void rig_write (int length, unsigned char buff[]);
5+void dvmega_read (void);
6+int read_dvmega(void);
7+
8+extern char RunState[];
9+
10+
11+void dvmega_write (int fd, unsigned char buff[], int length)
12+{
13+}
14+
15+void rig_buff_reset (int length)
16+{
17+ rig_buff_pnt -= length;
18+ memmove (rig_buff, &rig_buff[length], rig_buff_pnt);
19+}
20+
21+int send_dvmega_status(void)
22+{
23+ unsigned char buffer[3];
24+
25+ buffer[0] = DVMEGA_FRAME_START;
26+ buffer[1] = 3;
27+ buffer[2] = DVMEGA_GET_STATUS;
28+ gettimeofday (&dvmega_status_send, NULL);
29+ return write(rig_fd, buffer, 3U);
30+}
31+
32+void dvmega_init (void)
33+{
34+ /* get Version */
35+ unsigned char dvmega_get_version[3] = {0x0e, 0x03, 0x00};
36+
37+ rig_write (3, dvmega_get_version);
38+ time (&rig_init_time);
39+}
40+
41+int dvmega_init_recv (void)
42+{
43+ int length;
44+
45+ length = read_dvmega();
46+ syslog (LOG_INFO, "%d", length);
47+ if (length == 0) return FALSE;
48+ if (rig_buff[2] != DVMEGA_GER_VERSION) return FALSE;
49+ syslog (LOG_DEBUG, "%6.6s", &rig_buff[4]);
50+ rig_buff_reset (length);
51+ send_dvmega_status();
52+ return TRUE;
53+}
54+
55+void dvmega_read (void)
56+{
57+ int length;
58+ unsigned char pkt_type;
59+
60+ length = read_dvmega();
61+ if (length == 0) return;
62+ pkt_type = rig_buff[2];
63+
64+ switch (pkt_type)
65+ {
66+ case DVMEGA_ACK:
67+ dvmega_check_wait = TRUE;
68+ break;
69+ case DVMEGA_NAK:
70+ dvmega_check_wait = FALSE;
71+ break;
72+
73+ case DVMEGA_DSTAR_HEADER:
74+ syslog (LOG_DEBUG, "header %2.2x %d %2.2x", rig_buff[0], rig_buff[1], rig_buff[2]);
75+ break;
76+
77+ case DVMEGA_DSTAR_DATA:
78+ syslog (LOG_DEBUG, "data %2.2x %d %2.2x", rig_buff[0], rig_buff[1], rig_buff[2]);
79+ break;
80+
81+ case DVMEGA_DSTAR_LOST:
82+ syslog (LOG_DEBUG, "lost %2.2x %d %2.2x", rig_buff[0], rig_buff[1], rig_buff[2]);
83+
84+ break;
85+
86+ case DVMEGA_DSTAR_EOT:
87+syslog (LOG_DEBUG, "eot %2.2x %d %2.2x", rig_buff[0], rig_buff[1], rig_buff[2]);
88+ break;
89+
90+ case DVMEGA_GET_STATUS:
91+syslog (LOG_DEBUG, "status %2.2x %d %2.2x", rig_buff[0], rig_buff[1], rig_buff[2]);
92+ dvmega_dstar_space = rig_buff[6];
93+ break;
94+
95+ default:
96+ return;
97+ }
98+ rig_buff_reset (length);
99+}
100+
101+int read_dvmega (void)
102+{
103+ int length;
104+ int i;
105+
106+ if (FD_ISSET (rig_fd, &read_set))
107+ {
108+ length = read (rig_fd, &rig_buff[rig_buff_pnt],
109+ sizeof(rig_buff) - rig_buff_pnt);
110+ if (length == -1)
111+ {
112+ syslog(LOG_ERR, "rig read error %s", strerror(errno));
113+ return 0;
114+ }
115+ if (length > 0)
116+ {
117+ rig_buff_pnt += length;
118+ for (i = 0 ; i < rig_buff_pnt ; i++)
119+ {
120+ if (rig_buff[i] == DVMEGA_FRAME_START)
121+ {
122+ rig_buff_pnt -= i;
123+ if (i > 0) memmove (rig_buff, &rig_buff[i], rig_buff_pnt);
124+ if (rig_buff_pnt > 2)
125+ {
126+ length = rig_buff[1];
127+ if (rig_buff_pnt >= length) return length;
128+ }
129+ return 0;
130+ }
131+ }
132+ rig_buff_pnt = 0;
133+ return 0;
134+ }
135+ }
136+ return 0;
137+}
138+
139+int dv_mega_readStatus()
140+{
141+ unsigned char buffer[3];
142+
143+ buffer[0U] = DVMEGA_FRAME_START;
144+ buffer[1U] = 3;
145+ buffer[2U] = DVMEGA_GET_STATUS;
146+
147+ return write(rig_fd, buffer, 3);
148+}
149+
150+int dvmega_setFrequency(void)
151+{
152+
153+ unsigned char buffer[20];
154+ unsigned char len;
155+
156+ buffer[0] = DVMEGA_FRAME_START;
157+ buffer[1] = 12;
158+ buffer[2] = DVMEGA_SET_FREQ;
159+ buffer[3] = 0x00;
160+ buffer[4] = (dvmega_rx_freq >> 0) & 0xFF;
161+ buffer[5] = (dvmega_rx_freq >> 8) & 0xFF;
162+ buffer[6] = (dvmega_rx_freq >> 16) & 0xFF;
163+ buffer[7] = (dvmega_rx_freq >> 24) & 0xFF;
164+ buffer[8] = (dvmega_tx_freq >> 0) & 0xFF;
165+ buffer[9] = (dvmega_tx_freq >> 8) & 0xFF;
166+ buffer[10] = (dvmega_tx_freq >> 16) & 0xFF;
167+ buffer[11] = (dvmega_tx_freq >> 24) & 0xFF;
168+
169+ int ret = write(rig_fd, buffer, len);
170+ if (ret != len)
171+ return FALSE;
172+ return TRUE;
173+}
174+
175+int dvmega_setMode(unsigned char mode)
176+{
177+ unsigned char buffer[4];
178+
179+ buffer[0] = DVMEGA_FRAME_START;
180+ buffer[1] = 4;
181+ buffer[2] = DVMEGA_SET_MODE;
182+ buffer[3] = mode;
183+
184+ return write(rig_fd, buffer, 4);
185+}
186+
187+void dvmega_close (void)
188+{
189+ ssize_t len;
190+
191+ RunState[4] = 0x00;
192+ len = write (rig_fd, RunState, 5);
193+ tcdrain (rig_fd);
194+ tcsetattr (rig_fd, TCSANOW, &save_attr);
195+ dvmega_NoRespReply_sw = FALSE;
196+ //dvap_skip();
197+ dvmega_gw_resp_sw = FALSE;
198+ dvmega_last_frame_sw = FALSE;
199+ dvmega_voice_send_sw = FALSE;
200+ if (dvmega_sw)
201+ {
202+ syslog (LOG_INFO, "DVMEGA down.");
203+ }
204+ dvmega_sw = FALSE;
205+ FD_CLR (rig_fd, &fd_save);
206+ close (rig_fd);
207+ rig_fd = 0;
208+}
--- a/main.c
+++ b/main.c
@@ -24,6 +24,7 @@ void dummy_last_frame (void);
2424 void jitter_buff_init (void);
2525 void jitter_putFifo (void);
2626 void dvap_conf(void);
27+void dvmega_conf (void);
2728 void dvap_read(void);
2829 int ETagGen (char file_name[], char md5[]);
2930 void error_msg(char str[]);
@@ -31,7 +32,7 @@ void error_msg_clean(void);
3132 void short_msg_wrt(void);
3233 void wait_disconnect (void);
3334 void send_msg (char str[], char my2[]);
34-
35+void dvmega_read(void);
3536
3637 time_t send_time;
3738 unsigned char *ppp;
@@ -98,6 +99,7 @@ int main(int argc, char *argv[])
9899 {
99100 bf = fgets (recvBuff, sizeof (recvBuff), RigType);
100101 if (!memcmp (recvBuff, "DVAP", 4)) rig_type = DVAP;
102+ else if (!memcmp (recvBuff, "DVMEGA", 6)) rig_type = DVMEGA;
101103 else rig_type = ICOM;
102104 fclose (RigType);
103105 }
@@ -221,7 +223,7 @@ int main(int argc, char *argv[])
221223 connected_table_clean();
222224 error_msg_clean();
223225
224- rig_buff_pnt = 0;
226+ //rig_buff_pnt = 0;
225227 rig_last_frame_send = TRUE;
226228
227229 jitter_buff_init();
@@ -231,7 +233,8 @@ int main(int argc, char *argv[])
231233
232234 hole_punch_send_cnt = 0;
233235
234- dvap_conf();
236+ if (rig_type == DVAP) dvap_conf();
237+ else if (rig_type == DVMEGA) dvmega_conf();
235238 dvap_send_header_sw = FALSE;
236239 dvap_first_voice_pkt = FALSE;
237240
@@ -272,9 +275,10 @@ top:
272275 {
273276 inet_read ();
274277 }
275- if ((rig_type == DVAP) && FD_ISSET (rig_fd, &read_set))
278+ if (FD_ISSET (rig_fd, &read_set))
276279 {
277- dvap_read();
280+ if (rig_type == DVAP) dvap_read();
281+ if (rig_type == DVMEGA) dvmega_read();
278282 }
279283 }
280284 jitter_putFifo();
--- a/rig_read.c
+++ b/rig_read.c
@@ -1,11 +1,12 @@
11 #include "dmonitor.h"
22 #include "dstar.h"
33 #include "dvap.h"
4+#include "dvmega.h"
45
56 void rig_close(void);
67 int inet_send_buff_set(void);
78 void inet_send_position_update (char call[]);
8-void send_rig_init (void);
9+void icom_init (void);
910 int rig_open (void);
1011 void sind_rig_alive (void);
1112 void icom_reinit (void);
@@ -16,21 +17,23 @@ int getFifo (char str[]);
1617 void jitter_buff_init (void);
1718 void dvap_init(void);
1819 void dvap (void);
20+void dvmega(void);
1921 int rig_read (void);
2022 void dvap_write (int fd, unsigned char buff[], int length);
23+void dvmega_write (int fd, unsigned char buff[], int length);
2124 void dstar_data (unsigned char string[], int inet);
2225 void short_msg_wrt (void);
2326 void rig_not_connect_msg (void);
27+void dvmega_init (void);
28+int dvmega_init_recv (void);
2429
2530 char init_pkt[] = {0xff, 0xff, 0xff};
2631 char alive[] = {0x02, 0x02, 0xff};
27-unsigned char rig_buff[1024];
28-unsigned char dvmega_init[3] = { 0xe0, 0x03, 0x00 };
2932
3033 time_t rig_alive_send_time;
3134 int rig_error_cnt;
3235
33-int rig_init_recv (void)
36+int icom_init_recv (void)
3437 {
3538 int length;
3639 int i;
@@ -109,8 +112,7 @@ void rig(void)
109112 break;
110113
111114 case RIG_OPEN:
112- if (!rig_open()) sig_term = TRUE;
113- else
115+ if (rig_open())
114116 {
115117 if (rig_type == ICOM) rig_state = ICOM_INIT;
116118 else if (rig_type == DVAP) rig_state = DVAP_INIT;
@@ -118,11 +120,13 @@ void rig(void)
118120 rig_error_cnt = 0;
119121 rig_buff_pnt = 0;
120122 }
123+ else
124+ sig_term = TRUE;
121125 break;
122126
123127 case ICOM_INIT:
124128 memset (inet_frame_id, 0xff, 2);
125- send_rig_init();
129+ icom_init();
126130 rig_state = ICOM_INIT_DONE;
127131 time (&rig_init_time);
128132 rig_alive_send_time = 0;
@@ -132,7 +136,7 @@ void rig(void)
132136 break;
133137
134138 case ICOM_INIT_DONE:
135- if (rig_init_recv())
139+ if (icom_init_recv())
136140 {
137141 rig_state = RIG_READ;
138142 syslog (LOG_INFO, "RIG(ID-xxPlus) init/re-init done");
@@ -198,7 +202,7 @@ void rig(void)
198202 break;
199203
200204 case DVMEGA_INIT:
201- send_rig_init();
205+ dvmega_init();
202206 rig_state = DVMEGA_INIT_DONE;
203207 time (&rig_init_time);
204208 rig_alive_send_time = 0;
@@ -208,10 +212,10 @@ void rig(void)
208212 break;
209213
210214 case DVMEGA_INIT_DONE:
211- if (rig_init_recv())
215+ if (dvmega_init_recv())
212216 {
213217 rig_state = RIG_READ;
214- syslog (LOG_INFO, "RIG(ID-xxPlus) init/re-init done");
218+ syslog (LOG_INFO, "RIG(DVMEGA) init/re-init done");
215219 memset (inet_frame_id, 0x00, 2);
216220 frameID = 0;
217221 rig_send_sw = FALSE;
@@ -225,8 +229,8 @@ void rig(void)
225229 time (&cur_time);
226230 if ((cur_time - rig_init_time) >= 2)
227231 {
228- if(!scan_sw) syslog (LOG_INFO, "RIG(ID-xxPlus) no resp.");
229- else fprintf (status_fd, "RIG(ID-xxPlus) no resp.\n");
232+ if(!scan_sw) syslog (LOG_INFO, "RIG(DVMEGA) no resp.");
233+ else fprintf (status_fd, "RIG(DVMEGA) no resp.\n");
230234 rig_close();
231235 rig_not_connect_msg();
232236 not_clear_error_msg = TRUE;
@@ -255,11 +259,8 @@ void rig(void)
255259 icom_reinit();
256260 }
257261 }
258- else if (rig_type == DVMEGA)
259- {
260- }
261- else
262- dvap();
262+ else if (rig_type == DVMEGA) dvmega();
263+ else if (rig_type == DVAP) dvap();
263264 break;
264265 }
265266 }
@@ -536,10 +537,14 @@ void rig_write (int length, unsigned char buff[])
536537 time (&rig_alive_send_time);
537538 tcdrain (rig_fd);
538539 }
539- else
540+ else if (rig_type == DVAP)
540541 {
541542 dvap_write (rig_fd, buff, length);
542543 }
544+ else if (rig_type == DVMEGA)
545+ {
546+ dvmega_write (rig_fd, buff, length);
547+ }
543548
544549 #ifdef _DEBUG_RIG
545550 syslog (LOG_INFO, "rig_write %d %d %2.2x %2.2x", length, ret, buff[2], buff[3]);
@@ -555,12 +560,11 @@ void rig_write (int length, unsigned char buff[])
555560 #endif
556561 }
557562
558-void send_rig_init (void)
563+void icom_init (void)
559564 {
560565 int len;
561566
562- if (rig_type == ICOM) rig_write (3, init_pkt);
563- else if (rig_type == DVMEGA) rig_write (3, dvmega_init);
567+ rig_write (3, init_pkt);
564568 time (&rig_init_time);
565569 }
566570
--- a/rpt_conn.h
+++ b/rpt_conn.h
@@ -36,6 +36,7 @@
3636 #define FALSE 0
3737
3838 #define DVAP_CONF "/var/www/dvap.conf"
39+#define DVMEGA_CONF "/var/www/dvmega.conf"
3940 #define RIG_DEVICE "/dev/dstar"
4041 #define RIG_FILE "/var/www/rig.type"
4142 #define CONNECT_CALL "/var/www/ConnectCall"