修訂. | 時間 | 作者 |
---|---|---|
e8f3f20 users/ahayward/variable_sve2 | 2018-11-08 00:16:30 | Alan Hayward |
Aarch64 SVE: Support changing vector lengths in gdbserver |
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7a9abb2 | 2018-11-08 00:16:30 | Alan Hayward |
Add gdbserver target methods target_validate_tdesc and arch_setup |
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03345b3 | 2018-11-08 00:16:29 | Alan Hayward |
Add target_description_changed_p and target_get_tdep_info methods |
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7df3140 | 2018-11-08 00:16:29 | Alan Hayward |
Name and seperate the union in gdbarch_info |
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7972cd8 | 2018-11-08 00:16:24 | Alan Hayward |
Aarch64 SVE: Support changing vector lengths in GDB |
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4bcad10 | 2018-11-08 00:16:09 | Alan Hayward |
Aarch64 SVE: Support changing vector lengths for ptrace |
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35ee2dc | 2018-11-07 21:58:56 | Andrew Burgess |
gdb: Guard against NULL dereference in dwarf2_init_integer_type |
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42d4c30 | 2018-11-07 20:25:06 | Alan Modra |
Regen bfd/configure |
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8d3c78e | 2018-11-07 17:18:05 | Yoshinori Sato |
rx: Add target rx-*-linux. |
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8f531a8 | 2018-11-07 09:00:16 | GDB Administrator |
Automatic date update in version.in |
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31aceee | 2018-11-07 07:15:41 | Tom de Vries |
[gdb] Fix gdb crash when reading core file |
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109be30 | 2018-11-07 04:06:23 | Jim Wilson |
RISC-V: Force variables to .data for code_elim. |
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f11acc5 | 2018-11-07 03:25:11 | Max Filippov |
gdb: xtensa: use linux ABI code for uclinux |
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9e23774 | 2018-11-07 02:54:08 | Marius Muench |
ARM: Do not use FP reg when on AAPCS |
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bcecc11 | 2018-11-07 02:47:21 | John Baldwin |
Note that PT_GETREGS supplies SSTATUS for FreeBSD/riscv. |
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8a6b075 | 2018-11-07 02:38:51 | H.J. Lu |
elfedit: Add --enable-x86-feature/--disable-x86-feature |
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ddea148 | 2018-11-07 02:17:43 | Nick Clifton |
Add support for a couple of new Mach-O commands. |
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f86e17a | 2018-11-07 02:09:34 | Matthew Malcomson |
[arm] fix testsuite breakage on pe-coff |
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bc52d49 | 2018-11-06 23:54:32 | Matthew Malcomson |
[arm] Check for neon and condition in vcvt.f16.f32 |
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0632eee | 2018-11-06 21:13:45 | Sudakshina Das |
[BINUTILS, ARM] Add Armv8.5-A to select_arm_features and update macros. |
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7155371 | 2018-11-06 19:47:28 | Alan Modra |
PowerPC instruction mask checks |
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2eac3da | 2018-11-06 19:47:28 | Alan Modra |
PowerPC instruction operand flag validation |
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4dd4e63 | 2018-11-06 19:45:49 | Jan Beulich |
x86: correctly handle VPBROADCASTD with EVEX.W set outside of 64-bit mode |
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9819647 | 2018-11-06 19:45:11 | Jan Beulich |
x86: correctly handle VMOVD with EVEX.W set outside of 64-bit mode |
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58a211d | 2018-11-06 19:44:31 | Jan Beulich |
x86: correctly handle KMOVD with VEX.W set outside of 64-bit mode |
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b50c9f3 | 2018-11-06 19:43:55 | Jan Beulich |
x86: adjust {,E}VEX.W handling for PEXTR* / PINSR* |
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931d03b | 2018-11-06 19:42:54 | Jan Beulich |
x86: adjust {,E}VEX.W handling outside of 64-bit mode |
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fd71a37 | 2018-11-06 19:42:08 | Jan Beulich |
x86: fix various non-LIG templates |
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563c7ee | 2018-11-06 19:40:25 | Jan Beulich |
x86: allow {store} to select alternative {,}PEXTRW encoding |
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0aaca1d | 2018-11-06 19:39:42 | Jan Beulich |
x86: add more VexWIG |