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GNU Binutils with patches for OS216


Commit MetaInfo

修訂322474019df79a1305e83ff7620a72f31a5c7b55 (tree)
時間2018-01-25 01:19:47
作者Renlin Li <renlin.li@arm....>
CommiterRenlin Li

Log Message

[GAS][AARCH64]Add group relocations to create PC-relative offset.

This is a patch to add the gas support for group relocations to create a
16, 32, 48, or 64 bit PC-relative offset inline.

The following relocations are added along with the test cases:
BFD_RELOC_AARCH64_MOVW_PREL_G0, BFD_RELOC_AARCH64_MOVW_PREL_G0_NC,
BFD_RELOC_AARCH64_MOVW_PREL_G1, BFD_RELOC_AARCH64_MOVW_PREL_G1_NC,
BFD_RELOC_AARCH64_MOVW_PREL_G2, BFD_RELOC_AARCH64_MOVW_PREL_G2_NC,
BFD_RELOC_AARCH64_MOVW_PREL_G3.

bfd/

2018-01-24 Renlin Li <renlin.li@arm.com>

* reloc.c: Add BFD_RELOC_AARCH64_MOVW_PREL_G0,
BFD_RELOC_AARCH64_MOVW_PREL_G0_NC, BFD_RELOC_AARCH64_MOVW_PREL_G1,
BFD_RELOC_AARCH64_MOVW_PREL_G1_NC, BFD_RELOC_AARCH64_MOVW_PREL_G2,
BFD_RELOC_AARCH64_MOVW_PREL_G2_NC, BFD_RELOC_AARCH64_MOVW_PREL_G3.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
* elfnn-aarch64.c (elfNN_aarch64_howto_table): Add entries for
BFD_RELOC_AARCH64_MOVW_PREL_G0, BFD_RELOC_AARCH64_MOVW_PREL_G0_NC,
BFD_RELOC_AARCH64_MOVW_PREL_G1, BFD_RELOC_AARCH64_MOVW_PREL_G1_NC,
BFD_RELOC_AARCH64_MOVW_PREL_G2, BFD_RELOC_AARCH64_MOVW_PREL_G2_NC,
BFD_RELOC_AARCH64_MOVW_PREL_G3.

gas/

2018-01-24 Renlin Li <renlin.li@arm.com>

* config/tc-aarch64.c (reloc_table): add entries for
BFD_RELOC_AARCH64_MOVW_PREL_G0, BFD_RELOC_AARCH64_MOVW_PREL_G0_NC,
BFD_RELOC_AARCH64_MOVW_PREL_G1, BFD_RELOC_AARCH64_MOVW_PREL_G1_NC,
BFD_RELOC_AARCH64_MOVW_PREL_G2, BFD_RELOC_AARCH64_MOVW_PREL_G2_NC,
BFD_RELOC_AARCH64_MOVW_PREL_G3.
(process_movw_reloc_info): Supports newly added MOVW_PREL relocations.
(md_apply_fix): Likewise
* testsuite/gas/aarch64/prel_g0.s: New.
* testsuite/gas/aarch64/prel_g0.d: New.
* testsuite/gas/aarch64/prel_g0_nc.s: New.
* testsuite/gas/aarch64/prel_g0_nc.d: New.
* testsuite/gas/aarch64/prel_g1.s: New.
* testsuite/gas/aarch64/prel_g1.d: New.
* testsuite/gas/aarch64/prel_g1_nc.s: New.
* testsuite/gas/aarch64/prel_g1_nc.d: New.
* testsuite/gas/aarch64/prel_g2.s: New.
* testsuite/gas/aarch64/prel_g2.d: New.
* testsuite/gas/aarch64/prel_g2_nc.s: New.
* testsuite/gas/aarch64/prel_g2_nc.d: New.
* testsuite/gas/aarch64/prel_g3.s: New.
* testsuite/gas/aarch64/prel_g3.d: New.

Change Summary

差異

--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,17 @@
1+2018-01-24 Renlin Li <renlin.li@arm.com>
2+
3+ * reloc.c: Add BFD_RELOC_AARCH64_MOVW_PREL_G0,
4+ BFD_RELOC_AARCH64_MOVW_PREL_G0_NC, BFD_RELOC_AARCH64_MOVW_PREL_G1,
5+ BFD_RELOC_AARCH64_MOVW_PREL_G1_NC, BFD_RELOC_AARCH64_MOVW_PREL_G2,
6+ BFD_RELOC_AARCH64_MOVW_PREL_G2_NC, BFD_RELOC_AARCH64_MOVW_PREL_G3.
7+ * elfnn-aarch64.c (elfNN_aarch64_howto_table): Add entries for
8+ BFD_RELOC_AARCH64_MOVW_PREL_G0, BFD_RELOC_AARCH64_MOVW_PREL_G0_NC,
9+ BFD_RELOC_AARCH64_MOVW_PREL_G1, BFD_RELOC_AARCH64_MOVW_PREL_G1_NC,
10+ BFD_RELOC_AARCH64_MOVW_PREL_G2, BFD_RELOC_AARCH64_MOVW_PREL_G2_NC,
11+ BFD_RELOC_AARCH64_MOVW_PREL_G3.
12+ * bfd-in2.h: Regenerate.
13+ * libbfd.h: Regenerate.
14+
115 2018-01-23 Maciej W. Rozycki <macro@mips.com>
216
317 * elfxx-mips.c (_bfd_mips_elf_final_link): Update a stale
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -5957,6 +5957,36 @@ of a signed value. Changes instruction to MOVZ or MOVN depending on the
59575957 value's sign. */
59585958 BFD_RELOC_AARCH64_MOVW_G2_S,
59595959
5960+/* AArch64 MOV[NZ] instruction with most significant bits 0 to 15
5961+of a signed value. Changes instruction to MOVZ or MOVN depending on the
5962+value's sign. */
5963+ BFD_RELOC_AARCH64_MOVW_PREL_G0,
5964+
5965+/* AArch64 MOV[NZ] instruction with most significant bits 0 to 15
5966+of a signed value. Changes instruction to MOVZ or MOVN depending on the
5967+value's sign. */
5968+ BFD_RELOC_AARCH64_MOVW_PREL_G0_NC,
5969+
5970+/* AArch64 MOVK instruction with most significant bits 16 to 31
5971+of a signed value. */
5972+ BFD_RELOC_AARCH64_MOVW_PREL_G1,
5973+
5974+/* AArch64 MOVK instruction with most significant bits 16 to 31
5975+of a signed value. */
5976+ BFD_RELOC_AARCH64_MOVW_PREL_G1_NC,
5977+
5978+/* AArch64 MOVK instruction with most significant bits 32 to 47
5979+of a signed value. */
5980+ BFD_RELOC_AARCH64_MOVW_PREL_G2,
5981+
5982+/* AArch64 MOVK instruction with most significant bits 32 to 47
5983+of a signed value. */
5984+ BFD_RELOC_AARCH64_MOVW_PREL_G2_NC,
5985+
5986+/* AArch64 MOVK instruction with most significant bits 47 to 63
5987+of a signed value. */
5988+ BFD_RELOC_AARCH64_MOVW_PREL_G3,
5989+
59605990 /* AArch64 Load Literal instruction, holding a 19 bit pc-relative word
59615991 offset. The lowest two bits must be zero and are not stored in the
59625992 instruction, giving a 21 bit signed byte offset. */
--- a/bfd/elfnn-aarch64.c
+++ b/bfd/elfnn-aarch64.c
@@ -617,6 +617,114 @@ static reloc_howto_type elfNN_aarch64_howto_table[] =
617617 0xffff, /* dst_mask */
618618 FALSE), /* pcrel_offset */
619619
620+ /* Group relocations to create a 16, 32, 48 or 64 bit
621+ PC relative address inline. */
622+
623+ /* MOV[NZ]: ((S+A-P) >> 0) & 0xffff */
624+ HOWTO64 (AARCH64_R (MOVW_PREL_G0), /* type */
625+ 0, /* rightshift */
626+ 2, /* size (0 = byte, 1 = short, 2 = long) */
627+ 17, /* bitsize */
628+ TRUE, /* pc_relative */
629+ 0, /* bitpos */
630+ complain_overflow_signed, /* complain_on_overflow */
631+ bfd_elf_generic_reloc, /* special_function */
632+ AARCH64_R_STR (MOVW_PREL_G0), /* name */
633+ FALSE, /* partial_inplace */
634+ 0xffff, /* src_mask */
635+ 0xffff, /* dst_mask */
636+ TRUE), /* pcrel_offset */
637+
638+ /* MOVK: ((S+A-P) >> 0) & 0xffff [no overflow check] */
639+ HOWTO64 (AARCH64_R (MOVW_PREL_G0_NC), /* type */
640+ 0, /* rightshift */
641+ 2, /* size (0 = byte, 1 = short, 2 = long) */
642+ 16, /* bitsize */
643+ TRUE, /* pc_relative */
644+ 0, /* bitpos */
645+ complain_overflow_dont, /* complain_on_overflow */
646+ bfd_elf_generic_reloc, /* special_function */
647+ AARCH64_R_STR (MOVW_PREL_G0_NC), /* name */
648+ FALSE, /* partial_inplace */
649+ 0xffff, /* src_mask */
650+ 0xffff, /* dst_mask */
651+ TRUE), /* pcrel_offset */
652+
653+ /* MOV[NZ]: ((S+A-P) >> 16) & 0xffff */
654+ HOWTO64 (AARCH64_R (MOVW_PREL_G1), /* type */
655+ 16, /* rightshift */
656+ 2, /* size (0 = byte, 1 = short, 2 = long) */
657+ 17, /* bitsize */
658+ TRUE, /* pc_relative */
659+ 0, /* bitpos */
660+ complain_overflow_signed, /* complain_on_overflow */
661+ bfd_elf_generic_reloc, /* special_function */
662+ AARCH64_R_STR (MOVW_PREL_G1), /* name */
663+ FALSE, /* partial_inplace */
664+ 0xffff, /* src_mask */
665+ 0xffff, /* dst_mask */
666+ TRUE), /* pcrel_offset */
667+
668+ /* MOVK: ((S+A-P) >> 16) & 0xffff [no overflow check] */
669+ HOWTO64 (AARCH64_R (MOVW_PREL_G1_NC), /* type */
670+ 16, /* rightshift */
671+ 2, /* size (0 = byte, 1 = short, 2 = long) */
672+ 16, /* bitsize */
673+ TRUE, /* pc_relative */
674+ 0, /* bitpos */
675+ complain_overflow_dont, /* complain_on_overflow */
676+ bfd_elf_generic_reloc, /* special_function */
677+ AARCH64_R_STR (MOVW_PREL_G1_NC), /* name */
678+ FALSE, /* partial_inplace */
679+ 0xffff, /* src_mask */
680+ 0xffff, /* dst_mask */
681+ TRUE), /* pcrel_offset */
682+
683+ /* MOV[NZ]: ((S+A-P) >> 32) & 0xffff */
684+ HOWTO64 (AARCH64_R (MOVW_PREL_G2), /* type */
685+ 32, /* rightshift */
686+ 2, /* size (0 = byte, 1 = short, 2 = long) */
687+ 17, /* bitsize */
688+ TRUE, /* pc_relative */
689+ 0, /* bitpos */
690+ complain_overflow_signed, /* complain_on_overflow */
691+ bfd_elf_generic_reloc, /* special_function */
692+ AARCH64_R_STR (MOVW_PREL_G2), /* name */
693+ FALSE, /* partial_inplace */
694+ 0xffff, /* src_mask */
695+ 0xffff, /* dst_mask */
696+ TRUE), /* pcrel_offset */
697+
698+ /* MOVK: ((S+A-P) >> 32) & 0xffff [no overflow check] */
699+ HOWTO64 (AARCH64_R (MOVW_PREL_G2_NC), /* type */
700+ 32, /* rightshift */
701+ 2, /* size (0 = byte, 1 = short, 2 = long) */
702+ 16, /* bitsize */
703+ TRUE, /* pc_relative */
704+ 0, /* bitpos */
705+ complain_overflow_dont, /* complain_on_overflow */
706+ bfd_elf_generic_reloc, /* special_function */
707+ AARCH64_R_STR (MOVW_PREL_G2_NC), /* name */
708+ FALSE, /* partial_inplace */
709+ 0xffff, /* src_mask */
710+ 0xffff, /* dst_mask */
711+ TRUE), /* pcrel_offset */
712+
713+ /* MOV[NZ]: ((S+A-P) >> 48) & 0xffff */
714+ HOWTO64 (AARCH64_R (MOVW_PREL_G3), /* type */
715+ 48, /* rightshift */
716+ 2, /* size (0 = byte, 1 = short, 2 = long) */
717+ 16, /* bitsize */
718+ TRUE, /* pc_relative */
719+ 0, /* bitpos */
720+ complain_overflow_dont, /* complain_on_overflow */
721+ bfd_elf_generic_reloc, /* special_function */
722+ AARCH64_R_STR (MOVW_PREL_G3), /* name */
723+ FALSE, /* partial_inplace */
724+ 0xffff, /* src_mask */
725+ 0xffff, /* dst_mask */
726+ TRUE), /* pcrel_offset */
727+
620728 /* Relocations to generate 19, 21 and 33 bit PC-relative load/store
621729 addresses: PG(x) is (x & ~0xfff). */
622730
--- a/bfd/libbfd.h
+++ b/bfd/libbfd.h
@@ -2887,6 +2887,13 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
28872887 "BFD_RELOC_AARCH64_MOVW_G0_S",
28882888 "BFD_RELOC_AARCH64_MOVW_G1_S",
28892889 "BFD_RELOC_AARCH64_MOVW_G2_S",
2890+ "BFD_RELOC_AARCH64_MOVW_PREL_G0",
2891+ "BFD_RELOC_AARCH64_MOVW_PREL_G0_NC",
2892+ "BFD_RELOC_AARCH64_MOVW_PREL_G1",
2893+ "BFD_RELOC_AARCH64_MOVW_PREL_G1_NC",
2894+ "BFD_RELOC_AARCH64_MOVW_PREL_G2",
2895+ "BFD_RELOC_AARCH64_MOVW_PREL_G2_NC",
2896+ "BFD_RELOC_AARCH64_MOVW_PREL_G3",
28902897 "BFD_RELOC_AARCH64_LD_LO19_PCREL",
28912898 "BFD_RELOC_AARCH64_ADR_LO21_PCREL",
28922899 "BFD_RELOC_AARCH64_ADR_HI21_PCREL",
--- a/bfd/reloc.c
+++ b/bfd/reloc.c
@@ -7071,6 +7071,43 @@ ENUMDOC
70717071 of a signed value. Changes instruction to MOVZ or MOVN depending on the
70727072 value's sign.
70737073 ENUM
7074+ BFD_RELOC_AARCH64_MOVW_PREL_G0
7075+ENUMDOC
7076+ AArch64 MOV[NZ] instruction with most significant bits 0 to 15
7077+ of a signed value. Changes instruction to MOVZ or MOVN depending on the
7078+ value's sign.
7079+ENUM
7080+ BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
7081+ENUMDOC
7082+ AArch64 MOV[NZ] instruction with most significant bits 0 to 15
7083+ of a signed value. Changes instruction to MOVZ or MOVN depending on the
7084+ value's sign.
7085+ENUM
7086+ BFD_RELOC_AARCH64_MOVW_PREL_G1
7087+ENUMDOC
7088+ AArch64 MOVK instruction with most significant bits 16 to 31
7089+ of a signed value.
7090+ENUM
7091+ BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
7092+ENUMDOC
7093+ AArch64 MOVK instruction with most significant bits 16 to 31
7094+ of a signed value.
7095+ENUM
7096+ BFD_RELOC_AARCH64_MOVW_PREL_G2
7097+ENUMDOC
7098+ AArch64 MOVK instruction with most significant bits 32 to 47
7099+ of a signed value.
7100+ENUM
7101+ BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
7102+ENUMDOC
7103+ AArch64 MOVK instruction with most significant bits 32 to 47
7104+ of a signed value.
7105+ENUM
7106+ BFD_RELOC_AARCH64_MOVW_PREL_G3
7107+ENUMDOC
7108+ AArch64 MOVK instruction with most significant bits 47 to 63
7109+ of a signed value.
7110+ENUM
70747111 BFD_RELOC_AARCH64_LD_LO19_PCREL
70757112 ENUMDOC
70767113 AArch64 Load Literal instruction, holding a 19 bit pc-relative word
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,27 @@
1+2018-01-24 Renlin Li <renlin.li@arm.com>
2+
3+ * config/tc-aarch64.c (reloc_table): add entries for
4+ BFD_RELOC_AARCH64_MOVW_PREL_G0, BFD_RELOC_AARCH64_MOVW_PREL_G0_NC,
5+ BFD_RELOC_AARCH64_MOVW_PREL_G1, BFD_RELOC_AARCH64_MOVW_PREL_G1_NC,
6+ BFD_RELOC_AARCH64_MOVW_PREL_G2, BFD_RELOC_AARCH64_MOVW_PREL_G2_NC,
7+ BFD_RELOC_AARCH64_MOVW_PREL_G3.
8+ (process_movw_reloc_info): Supports newly added MOVW_PREL relocations.
9+ (md_apply_fix): Likewise
10+ * testsuite/gas/aarch64/prel_g0.s: New.
11+ * testsuite/gas/aarch64/prel_g0.d: New.
12+ * testsuite/gas/aarch64/prel_g0_nc.s: New.
13+ * testsuite/gas/aarch64/prel_g0_nc.d: New.
14+ * testsuite/gas/aarch64/prel_g1.s: New.
15+ * testsuite/gas/aarch64/prel_g1.d: New.
16+ * testsuite/gas/aarch64/prel_g1_nc.s: New.
17+ * testsuite/gas/aarch64/prel_g1_nc.d: New.
18+ * testsuite/gas/aarch64/prel_g2.s: New.
19+ * testsuite/gas/aarch64/prel_g2.d: New.
20+ * testsuite/gas/aarch64/prel_g2_nc.s: New.
21+ * testsuite/gas/aarch64/prel_g2_nc.d: New.
22+ * testsuite/gas/aarch64/prel_g3.s: New.
23+ * testsuite/gas/aarch64/prel_g3.d: New.
24+
125 2018-01-23 Maciej W. Rozycki <macro@mips.com>
226
327 * configure.ac: Also set `mips_default_abi' to N32_ABI for
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -2577,6 +2577,69 @@ static struct reloc_table_entry reloc_table[] = {
25772577 0,
25782578 0},
25792579
2580+ /* Most significant bits 0-15 of signed/unsigned address/value: MOVZ */
2581+ {"prel_g0", 1,
2582+ 0, /* adr_type */
2583+ 0,
2584+ BFD_RELOC_AARCH64_MOVW_PREL_G0,
2585+ 0,
2586+ 0,
2587+ 0},
2588+
2589+ /* Most significant bits 0-15 of signed/unsigned address/value: MOVK */
2590+ {"prel_g0_nc", 1,
2591+ 0, /* adr_type */
2592+ 0,
2593+ BFD_RELOC_AARCH64_MOVW_PREL_G0_NC,
2594+ 0,
2595+ 0,
2596+ 0},
2597+
2598+ /* Most significant bits 16-31 of signed/unsigned address/value: MOVZ */
2599+ {"prel_g1", 1,
2600+ 0, /* adr_type */
2601+ 0,
2602+ BFD_RELOC_AARCH64_MOVW_PREL_G1,
2603+ 0,
2604+ 0,
2605+ 0},
2606+
2607+ /* Most significant bits 16-31 of signed/unsigned address/value: MOVK */
2608+ {"prel_g1_nc", 1,
2609+ 0, /* adr_type */
2610+ 0,
2611+ BFD_RELOC_AARCH64_MOVW_PREL_G1_NC,
2612+ 0,
2613+ 0,
2614+ 0},
2615+
2616+ /* Most significant bits 32-47 of signed/unsigned address/value: MOVZ */
2617+ {"prel_g2", 1,
2618+ 0, /* adr_type */
2619+ 0,
2620+ BFD_RELOC_AARCH64_MOVW_PREL_G2,
2621+ 0,
2622+ 0,
2623+ 0},
2624+
2625+ /* Most significant bits 32-47 of signed/unsigned address/value: MOVK */
2626+ {"prel_g2_nc", 1,
2627+ 0, /* adr_type */
2628+ 0,
2629+ BFD_RELOC_AARCH64_MOVW_PREL_G2_NC,
2630+ 0,
2631+ 0,
2632+ 0},
2633+
2634+ /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2635+ {"prel_g3", 1,
2636+ 0, /* adr_type */
2637+ 0,
2638+ BFD_RELOC_AARCH64_MOVW_PREL_G3,
2639+ 0,
2640+ 0,
2641+ 0},
2642+
25802643 /* Get to the page containing GOT entry for a symbol. */
25812644 {"got", 1,
25822645 0, /* adr_type */
@@ -5079,6 +5142,10 @@ process_movw_reloc_info (void)
50795142 case BFD_RELOC_AARCH64_MOVW_G0_S:
50805143 case BFD_RELOC_AARCH64_MOVW_G1_S:
50815144 case BFD_RELOC_AARCH64_MOVW_G2_S:
5145+ case BFD_RELOC_AARCH64_MOVW_PREL_G0:
5146+ case BFD_RELOC_AARCH64_MOVW_PREL_G1:
5147+ case BFD_RELOC_AARCH64_MOVW_PREL_G2:
5148+ case BFD_RELOC_AARCH64_MOVW_PREL_G3:
50825149 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1:
50835150 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0:
50845151 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1:
@@ -5096,6 +5163,8 @@ process_movw_reloc_info (void)
50965163 case BFD_RELOC_AARCH64_MOVW_G0_NC:
50975164 case BFD_RELOC_AARCH64_MOVW_G0_S:
50985165 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC:
5166+ case BFD_RELOC_AARCH64_MOVW_PREL_G0:
5167+ case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC:
50995168 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC:
51005169 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC:
51015170 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC:
@@ -5109,6 +5178,8 @@ process_movw_reloc_info (void)
51095178 case BFD_RELOC_AARCH64_MOVW_G1_NC:
51105179 case BFD_RELOC_AARCH64_MOVW_G1_S:
51115180 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1:
5181+ case BFD_RELOC_AARCH64_MOVW_PREL_G1:
5182+ case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC:
51125183 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1:
51135184 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1:
51145185 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1:
@@ -5121,6 +5192,8 @@ process_movw_reloc_info (void)
51215192 case BFD_RELOC_AARCH64_MOVW_G2:
51225193 case BFD_RELOC_AARCH64_MOVW_G2_NC:
51235194 case BFD_RELOC_AARCH64_MOVW_G2_S:
5195+ case BFD_RELOC_AARCH64_MOVW_PREL_G2:
5196+ case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC:
51245197 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2:
51255198 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2:
51265199 if (is32)
@@ -5133,6 +5206,7 @@ process_movw_reloc_info (void)
51335206 shift = 32;
51345207 break;
51355208 case BFD_RELOC_AARCH64_MOVW_G3:
5209+ case BFD_RELOC_AARCH64_MOVW_PREL_G3:
51365210 if (is32)
51375211 {
51385212 set_fatal_syntax_error
@@ -7608,12 +7682,16 @@ md_apply_fix (fixS * fixP, valueT * valP, segT seg)
76087682 case BFD_RELOC_AARCH64_MOVW_G0_NC:
76097683 case BFD_RELOC_AARCH64_MOVW_G0_S:
76107684 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC:
7685+ case BFD_RELOC_AARCH64_MOVW_PREL_G0:
7686+ case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC:
76117687 scale = 0;
76127688 goto movw_common;
76137689 case BFD_RELOC_AARCH64_MOVW_G1:
76147690 case BFD_RELOC_AARCH64_MOVW_G1_NC:
76157691 case BFD_RELOC_AARCH64_MOVW_G1_S:
76167692 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1:
7693+ case BFD_RELOC_AARCH64_MOVW_PREL_G1:
7694+ case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC:
76177695 scale = 16;
76187696 goto movw_common;
76197697 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC:
@@ -7635,9 +7713,12 @@ md_apply_fix (fixS * fixP, valueT * valP, segT seg)
76357713 case BFD_RELOC_AARCH64_MOVW_G2:
76367714 case BFD_RELOC_AARCH64_MOVW_G2_NC:
76377715 case BFD_RELOC_AARCH64_MOVW_G2_S:
7716+ case BFD_RELOC_AARCH64_MOVW_PREL_G2:
7717+ case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC:
76387718 scale = 32;
76397719 goto movw_common;
76407720 case BFD_RELOC_AARCH64_MOVW_G3:
7721+ case BFD_RELOC_AARCH64_MOVW_PREL_G3:
76417722 scale = 48;
76427723 movw_common:
76437724 if (fixP->fx_done || !seg->use_rela_p)
@@ -7669,6 +7750,9 @@ md_apply_fix (fixS * fixP, valueT * valP, segT seg)
76697750 case BFD_RELOC_AARCH64_MOVW_G0_S:
76707751 case BFD_RELOC_AARCH64_MOVW_G1_S:
76717752 case BFD_RELOC_AARCH64_MOVW_G2_S:
7753+ case BFD_RELOC_AARCH64_MOVW_PREL_G0:
7754+ case BFD_RELOC_AARCH64_MOVW_PREL_G1:
7755+ case BFD_RELOC_AARCH64_MOVW_PREL_G2:
76727756 /* NOTE: We can only come here with movz or movn. */
76737757 if (signed_overflow (value, scale + 16))
76747758 as_bad_where (fixP->fx_file, fixP->fx_line,
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/reloc-prel_g0.d
@@ -0,0 +1,13 @@
1+#objdump: -dr
2+
3+.*: file format .*
4+
5+Disassembly of section \.text:
6+
7+0000000000000000 <.*>:
8+ 0: 8a000000 and x0, x0, x0
9+ 4: 92400000 and x0, x0, #0x1
10+ 8: d2800004 mov x4, #0x0 // #0
11+ 8: R_AARCH64_MOVW_PREL_G0 tempy
12+ c: d2800011 mov x17, #0x0 // #0
13+ c: R_AARCH64_MOVW_PREL_G0 tempy2
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/reloc-prel_g0.s
@@ -0,0 +1,7 @@
1+.comm gempy,4,4
2+.text
3+
4+ and x0,x0,x0
5+ and x0,x0,#0x1
6+ movz x4, :prel_g0:tempy
7+ movz x17, :prel_g0:tempy2
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/reloc-prel_g0_nc.d
@@ -0,0 +1,15 @@
1+#objdump: -dr
2+
3+.*: file format .*
4+
5+Disassembly of section \.text:
6+
7+0000000000000000 <.*>:
8+ 0: 8a000000 and x0, x0, x0
9+ 4: 92400000 and x0, x0, #0x1
10+ 8: f2800004 movk x4, #0x0
11+ 8: R_AARCH64_MOVW_PREL_G0_NC tempy
12+ c: f2800007 movk x7, #0x0
13+ c: R_AARCH64_MOVW_PREL_G0_NC tempy2
14+ 10: f2800011 movk x17, #0x0
15+ 10: R_AARCH64_MOVW_PREL_G0_NC tempy3
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/reloc-prel_g0_nc.s
@@ -0,0 +1,8 @@
1+.comm gempy,4,4
2+.text
3+
4+ and x0,x0,x0
5+ and x0,x0,#0x1
6+ movk x4, :prel_g0_nc:tempy
7+ movk x7, :prel_g0_nc:tempy2
8+ movk x17, :prel_g0_nc:tempy3
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/reloc-prel_g1.d
@@ -0,0 +1,13 @@
1+#objdump: -dr
2+
3+.*: file format .*
4+
5+Disassembly of section \.text:
6+
7+0000000000000000 <.*>:
8+ 0: 8a000000 and x0, x0, x0
9+ 4: 92400000 and x0, x0, #0x1
10+ 8: d2a00004 movz x4, #0x0, lsl #16
11+ 8: R_AARCH64_MOVW_PREL_G1 tempy
12+ c: d2a00011 movz x17, #0x0, lsl #16
13+ c: R_AARCH64_MOVW_PREL_G1 tempy2
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/reloc-prel_g1.s
@@ -0,0 +1,7 @@
1+.comm gempy,4,4
2+.text
3+
4+ and x0,x0,x0
5+ and x0,x0,#0x1
6+ movz x4, :prel_g1:tempy
7+ movz x17, :prel_g1:tempy2
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/reloc-prel_g1_nc.d
@@ -0,0 +1,15 @@
1+#objdump: -dr
2+
3+.*: file format .*
4+
5+Disassembly of section \.text:
6+
7+0000000000000000 <.*>:
8+ 0: 8a000000 and x0, x0, x0
9+ 4: 92400000 and x0, x0, #0x1
10+ 8: f2a00004 movk x4, #0x0, lsl #16
11+ 8: R_AARCH64_MOVW_PREL_G1_NC tempy
12+ c: f2a00007 movk x7, #0x0, lsl #16
13+ c: R_AARCH64_MOVW_PREL_G1_NC tempy2
14+ 10: f2a00011 movk x17, #0x0, lsl #16
15+ 10: R_AARCH64_MOVW_PREL_G1_NC tempy3
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/reloc-prel_g1_nc.s
@@ -0,0 +1,8 @@
1+.comm gempy,4,4
2+.text
3+
4+ and x0,x0,x0
5+ and x0,x0,#0x1
6+ movk x4, :prel_g1_nc:tempy
7+ movk x7, :prel_g1_nc:tempy2
8+ movk x17, :prel_g1_nc:tempy3
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/reloc-prel_g2.d
@@ -0,0 +1,15 @@
1+#objdump: -dr
2+
3+.*: file format .*
4+
5+Disassembly of section \.text:
6+
7+0000000000000000 <.*>:
8+ 0: 8a000000 and x0, x0, x0
9+ 4: 92400000 and x0, x0, #0x1
10+ 8: d2c00004 movz x4, #0x0, lsl #32
11+ 8: R_AARCH64_MOVW_PREL_G2 tempy
12+ c: d2c00007 movz x7, #0x0, lsl #32
13+ c: R_AARCH64_MOVW_PREL_G2 tempy2
14+ 10: d2c00011 movz x17, #0x0, lsl #32
15+ 10: R_AARCH64_MOVW_PREL_G2 tempy3
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/reloc-prel_g2.s
@@ -0,0 +1,8 @@
1+.comm gempy,4,4
2+.text
3+
4+ and x0,x0,x0
5+ and x0,x0,#0x1
6+ movz x4, :prel_g2:tempy
7+ movz x7, :prel_g2:tempy2
8+ movz x17, :prel_g2:tempy3
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/reloc-prel_g2_nc.d
@@ -0,0 +1,15 @@
1+#objdump: -dr
2+
3+.*: file format .*
4+
5+Disassembly of section \.text:
6+
7+0000000000000000 <.*>:
8+ 0: 8a000000 and x0, x0, x0
9+ 4: 92400000 and x0, x0, #0x1
10+ 8: f2c00004 movk x4, #0x0, lsl #32
11+ 8: R_AARCH64_MOVW_PREL_G2_NC tempy
12+ c: f2c00007 movk x7, #0x0, lsl #32
13+ c: R_AARCH64_MOVW_PREL_G2_NC tempy2
14+ 10: f2c00011 movk x17, #0x0, lsl #32
15+ 10: R_AARCH64_MOVW_PREL_G2_NC tempy3
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/reloc-prel_g2_nc.s
@@ -0,0 +1,8 @@
1+.comm gempy,4,4
2+.text
3+
4+ and x0,x0,x0
5+ and x0,x0,#0x1
6+ movk x4, :prel_g2_nc:tempy
7+ movk x7, :prel_g2_nc:tempy2
8+ movk x17, :prel_g2_nc:tempy3
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/reloc-prel_g3.d
@@ -0,0 +1,15 @@
1+#objdump: -dr
2+
3+.*: file format .*
4+
5+Disassembly of section \.text:
6+
7+0000000000000000 <.*>:
8+ 0: 8a000000 and x0, x0, x0
9+ 4: 92400000 and x0, x0, #0x1
10+ 8: d2e00004 movz x4, #0x0, lsl #48
11+ 8: R_AARCH64_MOVW_PREL_G3 tempy
12+ c: d2e00007 movz x7, #0x0, lsl #48
13+ c: R_AARCH64_MOVW_PREL_G3 tempy2
14+ 10: d2e00011 movz x17, #0x0, lsl #48
15+ 10: R_AARCH64_MOVW_PREL_G3 tempy3
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/reloc-prel_g3.s
@@ -0,0 +1,8 @@
1+.comm gempy,4,4
2+.text
3+
4+ and x0,x0,x0
5+ and x0,x0,#0x1
6+ movz x4, :prel_g3:tempy
7+ movz x7, :prel_g3:tempy2
8+ movz x17, :prel_g3:tempy3