Daniel Shapiro
dcsha****@gmail*****
2008年 4月 1日 (火) 13:19:05 JST
http://carg.site.uottawa.ca/literature.html On Tue, Apr 1, 2008 at 12:18 AM, Daniel Shapiro <dcsha****@gmail*****> wrote: > Hi All, > > Here is our high-level documentation. > > > On Mon, Mar 31, 2008 at 5:03 PM, Daniel Shapiro <dcsha****@gmail*****> > wrote: > > > Unfortunately, the message bounces from that mailing list when I include > > attachments, so below is the message again without the attachments: > > > > > > On Mon, Mar 31, 2008 at 5:00 PM, Daniel Shapiro <dcsha****@gmail*****> > > wrote: > > > > > Hi Sir, > > > > > > Sorry for the delay in response. I'm glad to provide you with our > > > documentation. We are working on multiprocessor systems on chip tools. I've > > > attached some posters we used to present our toolchain at a poster session. > > > At that point we were thinking about using GCC, but now that we have looked > > > closely, we think that COINS will be easier to use for our purposes. My > > > supervisor's name is Dr. Miodrag Bolic (http://site.uottawa.ca/~mbolic<http://site.uottawa.ca/%7Embolic>), > > > and we also have help from Prof Groza and his students ( > > > http://site.uottawa.ca/~groza/ <http://site.uottawa.ca/%7Egroza/>). > > > One important goal we have is to keep the tool open-source and accessible to > > > the wider community. > > > > > > We are trying to implement in COINS large new instructions like the > > > fuzzy logic block shown in the datapath in "carg_poster_fl.ppt". At first we > > > want to do this manually to get a feel for the structure of coins, and then > > > we want to add ISE identification. > > > > > > The concept of ISE identification may be familiar to you because of > > > the Xtensa processor backend from Tensilica. The instruction set extension > > > (ISE) identification problem is the search for a set of custom instructions > > > which can be added to a processor description without violating some > > > constraints such as area and power consumption. A sub-problem is to complete > > > the ISE identification without searching for too long. The searches tend to > > > be long because like many other compiler algorithms, the ISE identification > > > problem is NP-hard. And so many proposed solutions to large problems - such > > > as a large C program being compiled by GCC - are exact but return results > > > too slowly. We propose a heuristic in the form of an integer linear program. > > > We want to show the need for a mix of small instructions which are repeated > > > often, and large instructions which although rare provide a large speedup. > > > We propose a method for reducing the execution time of the solver by > > > allowing the compiler to define a cutoff execution time between improvements > > > in the solution, and a maximum execution time for the solver. Furthermore we > > > define the objective function as the number of cycles saved due to the > > > selection of custom instructions, because this measurement is additive. We > > > include in the ISE identification problem some local and global constraints > > > on code defined by the user. > > > > > > This semester we are using the LEON3 processor and adding a fuzzy > > > logic block to it. We want to use COINS to program the LEON3+fuzzy-logic > > > processor. Also, we are finishing up work on a multiprocessor interconnect > > > network generator written in java. It allows us to do simulation, design > > > space exploration, and VHDL implementation of multiprocessor systems. We are > > > just writing the paper for that now. My research group ( > > > carg.site.uottawa.ca) is funded by an NSERC grant from the government > > > of canada to research the following: > > > > > > It is becoming increasingly difficult to design systems on chip (SoC) > > > due to their high complexity and > > > increasing design requirements. Processing requirements of the > > > majority of applications are growing and cannot > > > be solved by single embedded processors, but by extending the systems > > > with customized configurable or > > > reconfigurable hardware (HW) or designing multiprocessing systems. > > > Existent SoC design flows require highly > > > qualified specialists, with proficiency in both HW and SW, to collect > > > system requirements and to make > > > structural decisions. Given the significant number of design choices, > > > the only possible options to address these > > > problems are automatic exploration of the design space and intelligent > > > acquisition of design requirements. > > > The main objective of this complex far-reaching project is to develop > > > a methodology and tools to automate the > > > SoC design based on configurable and reconfigurable single and > > > multi-processors. Our final goals of the > > > project, whose essential modules will be developed here, are to > > > develop a framework that will automatically > > > generate a multiprocessor system with custom instructions implemented > > > using configurable and reconfigurable > > > hardware that satisfies user requirements. We will focus on issues > > > related to real-time applications where a set > > > of timing and area constraints is imposed on the implementation. > > > Furthermore we aim to completely abstract > > > the complexities of this compilation process from the user, and, > > > instead, to collect requirements through an > > > intelligent user interface in an integrated development environment. > > > Our approach is to formulate the design > > > task as a series of optimization problems and to develop efficient > > > methods to solve them. We will also > > > concentrate on design steps at the system level, such as design space > > > exploration, automated generation of > > > custom instructions, architecture selection, performance estimation, > > > and selection between configurable or > > > reconfigurable architectures. As a part of this project, research on > > > multiprocessor systems with configurable > > > and reconfigurable capabilities will be pursued. Numerous Canadian > > > companies will be interested in the > > > increased productivity associated with our system. > > > > > > I can provide you with more information if you have any questions. In > > > summary, we are tinkering with COINS, trying to add large custom > > > instructions. Anyone who has a minute to chat can call me on skype. My > > > screen name is dcshapiro. > > > > > > Thanks for listening, > > > > > > > > > > > > On Fri, Mar 28, 2008 at 9:36 PM, nakata <nakat****@kamak*****> > > > wrote: > > > > > > > Dear Daniel, > > > > > > > > I'd like to know the details of your project. > > > > Can I read your documentation ? > > > > > > > > Thanks, > > > > > > > > Ikuo Nakata > > > > > > > > At 11:41 AM -0400 08.3.28, Daniel Shapiro wrote: > > > > > > > > Hi, > > > > > > > > I'm part of a project at the University of Ottawa that is trying to > > > > add instruction set extension to COINS. We are trying first manually, and > > > > then from basic-block analysis. Three of us are working right now at the > > > > LIR/TMD level and trying to add a large instruction manually to the SPARC > > > > ISA. We've been through the documentation and the code for the SPARC > > > > backend, and we've built a few simple compiler drivers. Is there anyone in > > > > the COINS project who might be able/interested in talking to us about COINS > > > > and how we might be able to contribute in this direction? > > > > > > > > Thanks, > > > > > > > > -- > > > > Daniel Shapiro, B.A.Sc ., M.A.Sc. (Candidate) > > > > > > > > School of Information Technology and Engineering (SITE), University > > > > of Ottawa > > > > Tel: (613) 562-5800 ext. 2189 > > > > Office: SITE4009 > > > > Email: dshap092 -at- site.uottawa.ca > > > > Website: site.uottawa.ca/~dshap092/<http://site.uottawa.ca/%7Edshap092/> > > > > Research Group: carg.site.uottawa.ca/ > > > > > > > > > > > > _______________________________________________ > > > > Coins-compiler-users mailing list > > > > Coins****@lists***** > > > > > > > > http://lists.sourceforge.jp/mailman/listinfo/coins-compiler-users > > > > > > > > > > > > -- > > > > > > > > Ikuo Nakata > > > > E-mail: nakat****@kamak***** > > > > > > > > > > > > > > > > -- > > > Daniel Shapiro, B.A.Sc ., M.A.Sc. (Candidate) > > > > > > School of Information Technology and Engineering (SITE), University of > > > Ottawa > > > Tel: (613) 562-5800 ext. 2189 > > > Office: SITE4009 > > > Email: dshap092 -at- site.uottawa.ca > > > Website: site.uottawa.ca/~dshap092/<http://site.uottawa.ca/%7Edshap092/> > > > Research Group: carg.site.uottawa.ca/ > > > > > > > > > > > -- > > Daniel Shapiro, B.A.Sc ., M.A.Sc. (Candidate) > > > > School of Information Technology and Engineering (SITE), University of > > Ottawa > > Tel: (613) 562-5800 ext. 2189 > > Office: SITE4009 > > Email: dshap092 -at- site.uottawa.ca > > Website: site.uottawa.ca/~dshap092/<http://site.uottawa.ca/%7Edshap092/> > > Research Group: carg.site.uottawa.ca/ > > > > > > -- > Daniel Shapiro, B.A.Sc ., M.A.Sc. (Candidate) > > School of Information Technology and Engineering (SITE), University of > Ottawa > Tel: (613) 562-5800 ext. 2189 > Office: SITE4009 > Email: dshap092 -at- site.uottawa.ca > Website: site.uottawa.ca/~dshap092/ <http://site.uottawa.ca/%7Edshap092/> > Research Group: carg.site.uottawa.ca/ > -- Daniel Shapiro, B.A.Sc ., M.A.Sc. (Candidate) School of Information Technology and Engineering (SITE), University of Ottawa Tel: (613) 562-5800 ext. 2189 Office: SITE4009 Email: dshap092 -at- site.uottawa.ca Website: site.uottawa.ca/~dshap092/ Research Group: carg.site.uottawa.ca/ -------------- next part -------------- HTML$B$NE:IU%U%!%$%k$rJ]4I$7$^$7$?(B...下載
