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stmole32exa: 提交

ライブラリ stmole32 を使用するサンプルプロジェクト


Commit MetaInfo

修訂1a9006b331e25b140af0f39d7be14095553ed570 (tree)
時間2020-11-07 17:35:56
作者molelord <molelord@user...>
Commitermolelord

Log Message

Add CubeMXが自動生成したソースをリポジトリへ追加

チケット 40895 に関連
CubeMX自体のバグやFWライブラリのバグのせいで、無修正な状態だとビルドに失敗することがある。そのため、あとで差分が分かるようにまず無修正の状態でリポジトリへ追加する。

Change Summary

差異

--- /dev/null
+++ b/gme_ws01/nuc-f429-blink/Core/Inc/main.h
@@ -0,0 +1,130 @@
1+/* USER CODE BEGIN Header */
2+/**
3+ ******************************************************************************
4+ * @file : main.h
5+ * @brief : Header for main.c file.
6+ * This file contains the common defines of the application.
7+ ******************************************************************************
8+ * @attention
9+ *
10+ * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
11+ * All rights reserved.</center></h2>
12+ *
13+ * This software component is licensed by ST under BSD 3-Clause license,
14+ * the "License"; You may not use this file except in compliance with the
15+ * License. You may obtain a copy of the License at:
16+ * opensource.org/licenses/BSD-3-Clause
17+ *
18+ ******************************************************************************
19+ */
20+/* USER CODE END Header */
21+
22+/* Define to prevent recursive inclusion -------------------------------------*/
23+#ifndef __MAIN_H
24+#define __MAIN_H
25+
26+#ifdef __cplusplus
27+extern "C" {
28+#endif
29+
30+/* Includes ------------------------------------------------------------------*/
31+#include "stm32f4xx_hal.h"
32+#include "stm32f4xx_ll_system.h"
33+#include "stm32f4xx_ll_gpio.h"
34+#include "stm32f4xx_ll_exti.h"
35+#include "stm32f4xx_ll_bus.h"
36+#include "stm32f4xx_ll_cortex.h"
37+#include "stm32f4xx_ll_rcc.h"
38+#include "stm32f4xx_ll_utils.h"
39+#include "stm32f4xx_ll_pwr.h"
40+#include "stm32f4xx_ll_dma.h"
41+
42+/* Private includes ----------------------------------------------------------*/
43+/* USER CODE BEGIN Includes */
44+
45+/* USER CODE END Includes */
46+
47+/* Exported types ------------------------------------------------------------*/
48+/* USER CODE BEGIN ET */
49+
50+/* USER CODE END ET */
51+
52+/* Exported constants --------------------------------------------------------*/
53+/* USER CODE BEGIN EC */
54+
55+/* USER CODE END EC */
56+
57+/* Exported macro ------------------------------------------------------------*/
58+/* USER CODE BEGIN EM */
59+
60+/* USER CODE END EM */
61+
62+/* Exported functions prototypes ---------------------------------------------*/
63+void Error_Handler(void);
64+
65+/* USER CODE BEGIN EFP */
66+
67+/* USER CODE END EFP */
68+
69+/* Private defines -----------------------------------------------------------*/
70+#define USER_Btn_Pin LL_GPIO_PIN_13
71+#define USER_Btn_GPIO_Port GPIOC
72+#define MCO_Pin LL_GPIO_PIN_0
73+#define MCO_GPIO_Port GPIOH
74+#define RMII_MDC_Pin LL_GPIO_PIN_1
75+#define RMII_MDC_GPIO_Port GPIOC
76+#define RMII_REF_CLK_Pin LL_GPIO_PIN_1
77+#define RMII_REF_CLK_GPIO_Port GPIOA
78+#define RMII_MDIO_Pin LL_GPIO_PIN_2
79+#define RMII_MDIO_GPIO_Port GPIOA
80+#define RMII_CRS_DV_Pin LL_GPIO_PIN_7
81+#define RMII_CRS_DV_GPIO_Port GPIOA
82+#define RMII_RXD0_Pin LL_GPIO_PIN_4
83+#define RMII_RXD0_GPIO_Port GPIOC
84+#define RMII_RXD1_Pin LL_GPIO_PIN_5
85+#define RMII_RXD1_GPIO_Port GPIOC
86+#define LD1_Pin LL_GPIO_PIN_0
87+#define LD1_GPIO_Port GPIOB
88+#define RMII_TXD1_Pin LL_GPIO_PIN_13
89+#define RMII_TXD1_GPIO_Port GPIOB
90+#define LD3_Pin LL_GPIO_PIN_14
91+#define LD3_GPIO_Port GPIOB
92+#define STLK_RX_Pin LL_GPIO_PIN_8
93+#define STLK_RX_GPIO_Port GPIOD
94+#define STLK_TX_Pin LL_GPIO_PIN_9
95+#define STLK_TX_GPIO_Port GPIOD
96+#define USB_PowerSwitchOn_Pin LL_GPIO_PIN_6
97+#define USB_PowerSwitchOn_GPIO_Port GPIOG
98+#define USB_OverCurrent_Pin LL_GPIO_PIN_7
99+#define USB_OverCurrent_GPIO_Port GPIOG
100+#define USB_SOF_Pin LL_GPIO_PIN_8
101+#define USB_SOF_GPIO_Port GPIOA
102+#define USB_VBUS_Pin LL_GPIO_PIN_9
103+#define USB_VBUS_GPIO_Port GPIOA
104+#define USB_ID_Pin LL_GPIO_PIN_10
105+#define USB_ID_GPIO_Port GPIOA
106+#define USB_DM_Pin LL_GPIO_PIN_11
107+#define USB_DM_GPIO_Port GPIOA
108+#define USB_DP_Pin LL_GPIO_PIN_12
109+#define USB_DP_GPIO_Port GPIOA
110+#define TMS_Pin LL_GPIO_PIN_13
111+#define TMS_GPIO_Port GPIOA
112+#define TCK_Pin LL_GPIO_PIN_14
113+#define TCK_GPIO_Port GPIOA
114+#define RMII_TX_EN_Pin LL_GPIO_PIN_11
115+#define RMII_TX_EN_GPIO_Port GPIOG
116+#define RMII_TXD0_Pin LL_GPIO_PIN_13
117+#define RMII_TXD0_GPIO_Port GPIOG
118+#define LD2_Pin LL_GPIO_PIN_7
119+#define LD2_GPIO_Port GPIOB
120+/* USER CODE BEGIN Private defines */
121+
122+/* USER CODE END Private defines */
123+
124+#ifdef __cplusplus
125+}
126+#endif
127+
128+#endif /* __MAIN_H */
129+
130+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null
+++ b/gme_ws01/nuc-f429-blink/Core/Inc/stm32_assert.h
@@ -0,0 +1,53 @@
1+/**
2+ ******************************************************************************
3+ * @file stm32_assert.h
4+ * @brief STM32 assert file.
5+ ******************************************************************************
6+ * @attention
7+ *
8+ * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
9+ * All rights reserved.</center></h2>
10+ *
11+ * This software component is licensed by ST under BSD 3-Clause license,
12+ * the "License"; You may not use this file except in compliance with the
13+ * License. You may obtain a copy of the License at:
14+ * opensource.org/licenses/BSD-3-Clause
15+ *
16+ ******************************************************************************
17+ */
18+
19+/* Define to prevent recursive inclusion -------------------------------------*/
20+#ifndef __STM32_ASSERT_H
21+#define __STM32_ASSERT_H
22+
23+#ifdef __cplusplus
24+ extern "C" {
25+#endif
26+
27+/* Exported types ------------------------------------------------------------*/
28+/* Exported constants --------------------------------------------------------*/
29+/* Includes ------------------------------------------------------------------*/
30+/* Exported macro ------------------------------------------------------------*/
31+#ifdef USE_FULL_ASSERT
32+/**
33+ * @brief The assert_param macro is used for function's parameters check.
34+ * @param expr: If expr is false, it calls assert_failed function
35+ * which reports the name of the source file and the source
36+ * line number of the call that failed.
37+ * If expr is true, it returns no value.
38+ * @retval None
39+ */
40+ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
41+/* Exported functions ------------------------------------------------------- */
42+ void assert_failed(uint8_t* file, uint32_t line);
43+#else
44+ #define assert_param(expr) ((void)0U)
45+#endif /* USE_FULL_ASSERT */
46+
47+#ifdef __cplusplus
48+}
49+#endif
50+
51+#endif /* __STM32_ASSERT_H */
52+
53+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null
+++ b/gme_ws01/nuc-f429-blink/Core/Inc/stm32f4xx_hal_conf.h
@@ -0,0 +1,486 @@
1+/**
2+ ******************************************************************************
3+ * @file stm32f4xx_hal_conf_template.h
4+ * @author MCD Application Team
5+ * @brief HAL configuration template file.
6+ * This file should be copied to the application folder and renamed
7+ * to stm32f4xx_hal_conf.h.
8+ ******************************************************************************
9+ * @attention
10+ *
11+ * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
12+ * All rights reserved.</center></h2>
13+ *
14+ * This software component is licensed by ST under BSD 3-Clause license,
15+ * the "License"; You may not use this file except in compliance with the
16+ * License. You may obtain a copy of the License at:
17+ * opensource.org/licenses/BSD-3-Clause
18+ *
19+ ******************************************************************************
20+ */
21+
22+/* Define to prevent recursive inclusion -------------------------------------*/
23+#ifndef __STM32F4xx_HAL_CONF_H
24+#define __STM32F4xx_HAL_CONF_H
25+
26+#ifdef __cplusplus
27+ extern "C" {
28+#endif
29+
30+/* Exported types ------------------------------------------------------------*/
31+/* Exported constants --------------------------------------------------------*/
32+
33+/* ########################## Module Selection ############################## */
34+/**
35+ * @brief This is the list of modules to be used in the HAL driver
36+ */
37+#define HAL_MODULE_ENABLED
38+
39+ /* #define HAL_ADC_MODULE_ENABLED */
40+/* #define HAL_CRYP_MODULE_ENABLED */
41+/* #define HAL_CAN_MODULE_ENABLED */
42+/* #define HAL_CRC_MODULE_ENABLED */
43+/* #define HAL_CAN_LEGACY_MODULE_ENABLED */
44+/* #define HAL_CRYP_MODULE_ENABLED */
45+/* #define HAL_DAC_MODULE_ENABLED */
46+/* #define HAL_DCMI_MODULE_ENABLED */
47+/* #define HAL_DMA2D_MODULE_ENABLED */
48+/* #define HAL_ETH_MODULE_ENABLED */
49+/* #define HAL_NAND_MODULE_ENABLED */
50+/* #define HAL_NOR_MODULE_ENABLED */
51+/* #define HAL_PCCARD_MODULE_ENABLED */
52+/* #define HAL_SRAM_MODULE_ENABLED */
53+/* #define HAL_SDRAM_MODULE_ENABLED */
54+/* #define HAL_HASH_MODULE_ENABLED */
55+/* #define HAL_I2C_MODULE_ENABLED */
56+/* #define HAL_I2S_MODULE_ENABLED */
57+/* #define HAL_IWDG_MODULE_ENABLED */
58+/* #define HAL_LTDC_MODULE_ENABLED */
59+/* #define HAL_RNG_MODULE_ENABLED */
60+/* #define HAL_RTC_MODULE_ENABLED */
61+/* #define HAL_SAI_MODULE_ENABLED */
62+/* #define HAL_SD_MODULE_ENABLED */
63+/* #define HAL_MMC_MODULE_ENABLED */
64+/* #define HAL_SPI_MODULE_ENABLED */
65+/* #define HAL_TIM_MODULE_ENABLED */
66+/* #define HAL_UART_MODULE_ENABLED */
67+/* #define HAL_USART_MODULE_ENABLED */
68+/* #define HAL_IRDA_MODULE_ENABLED */
69+/* #define HAL_SMARTCARD_MODULE_ENABLED */
70+/* #define HAL_SMBUS_MODULE_ENABLED */
71+/* #define HAL_WWDG_MODULE_ENABLED */
72+/* #define HAL_PCD_MODULE_ENABLED */
73+/* #define HAL_HCD_MODULE_ENABLED */
74+/* #define HAL_DSI_MODULE_ENABLED */
75+/* #define HAL_QSPI_MODULE_ENABLED */
76+/* #define HAL_QSPI_MODULE_ENABLED */
77+/* #define HAL_CEC_MODULE_ENABLED */
78+/* #define HAL_FMPI2C_MODULE_ENABLED */
79+/* #define HAL_SPDIFRX_MODULE_ENABLED */
80+/* #define HAL_DFSDM_MODULE_ENABLED */
81+/* #define HAL_LPTIM_MODULE_ENABLED */
82+#define HAL_GPIO_MODULE_ENABLED
83+#define HAL_EXTI_MODULE_ENABLED
84+#define HAL_DMA_MODULE_ENABLED
85+#define HAL_RCC_MODULE_ENABLED
86+#define HAL_FLASH_MODULE_ENABLED
87+#define HAL_PWR_MODULE_ENABLED
88+#define HAL_CORTEX_MODULE_ENABLED
89+
90+/* ########################## HSE/HSI Values adaptation ##################### */
91+/**
92+ * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
93+ * This value is used by the RCC HAL module to compute the system frequency
94+ * (when HSE is used as system clock source, directly or through the PLL).
95+ */
96+#if !defined (HSE_VALUE)
97+ #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
98+#endif /* HSE_VALUE */
99+
100+#if !defined (HSE_STARTUP_TIMEOUT)
101+ #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */
102+#endif /* HSE_STARTUP_TIMEOUT */
103+
104+/**
105+ * @brief Internal High Speed oscillator (HSI) value.
106+ * This value is used by the RCC HAL module to compute the system frequency
107+ * (when HSI is used as system clock source, directly or through the PLL).
108+ */
109+#if !defined (HSI_VALUE)
110+ #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
111+#endif /* HSI_VALUE */
112+
113+/**
114+ * @brief Internal Low Speed oscillator (LSI) value.
115+ */
116+#if !defined (LSI_VALUE)
117+ #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/
118+#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
119+ The real value may vary depending on the variations
120+ in voltage and temperature.*/
121+/**
122+ * @brief External Low Speed oscillator (LSE) value.
123+ */
124+#if !defined (LSE_VALUE)
125+ #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External Low Speed oscillator in Hz */
126+#endif /* LSE_VALUE */
127+
128+#if !defined (LSE_STARTUP_TIMEOUT)
129+ #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */
130+#endif /* LSE_STARTUP_TIMEOUT */
131+
132+/**
133+ * @brief External clock source for I2S peripheral
134+ * This value is used by the I2S HAL module to compute the I2S clock source
135+ * frequency, this source is inserted directly through I2S_CKIN pad.
136+ */
137+#if !defined (EXTERNAL_CLOCK_VALUE)
138+ #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the External audio frequency in Hz*/
139+#endif /* EXTERNAL_CLOCK_VALUE */
140+
141+/* Tip: To avoid modifying this file each time you need to use different HSE,
142+ === you can define the HSE value in your toolchain compiler preprocessor. */
143+
144+/* ########################### System Configuration ######################### */
145+/**
146+ * @brief This is the HAL system configuration section
147+ */
148+#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */
149+#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */
150+#define USE_RTOS 0U
151+#define PREFETCH_ENABLE 1U
152+#define INSTRUCTION_CACHE_ENABLE 1U
153+#define DATA_CACHE_ENABLE 1U
154+
155+#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */
156+#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */
157+#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */
158+#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */
159+#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */
160+#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */
161+#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */
162+#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */
163+#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */
164+#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */
165+#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */
166+#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */
167+#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */
168+#define USE_HAL_FMPI2C_REGISTER_CALLBACKS 0U /* FMPI2C register callback disabled */
169+#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */
170+#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */
171+#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */
172+#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */
173+#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */
174+#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */
175+#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */
176+#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */
177+#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */
178+#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */
179+#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */
180+#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */
181+#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */
182+#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */
183+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */
184+#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */
185+#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */
186+#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */
187+#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */
188+#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */
189+#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */
190+#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */
191+#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */
192+#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */
193+
194+/* ########################## Assert Selection ############################## */
195+/**
196+ * @brief Uncomment the line below to expanse the "assert_param" macro in the
197+ * HAL drivers code
198+ */
199+ #define USE_FULL_ASSERT 1U
200+
201+/* ################## Ethernet peripheral configuration ##################### */
202+
203+/* Section 1 : Ethernet peripheral configuration */
204+
205+/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
206+#define MAC_ADDR0 2U
207+#define MAC_ADDR1 0U
208+#define MAC_ADDR2 0U
209+#define MAC_ADDR3 0U
210+#define MAC_ADDR4 0U
211+#define MAC_ADDR5 0U
212+
213+/* Definition of the Ethernet driver buffers size and count */
214+#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
215+#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
216+#define ETH_RXBUFNB ((uint32_t)4U) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
217+#define ETH_TXBUFNB ((uint32_t)4U) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
218+
219+/* Section 2: PHY configuration section */
220+
221+/* DP83848_PHY_ADDRESS Address*/
222+#define DP83848_PHY_ADDRESS 0x01U
223+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
224+#define PHY_RESET_DELAY ((uint32_t)0x000000FFU)
225+/* PHY Configuration delay */
226+#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU)
227+
228+#define PHY_READ_TO ((uint32_t)0x0000FFFFU)
229+#define PHY_WRITE_TO ((uint32_t)0x0000FFFFU)
230+
231+/* Section 3: Common PHY Registers */
232+
233+#define PHY_BCR ((uint16_t)0x0000U) /*!< Transceiver Basic Control Register */
234+#define PHY_BSR ((uint16_t)0x0001U) /*!< Transceiver Basic Status Register */
235+
236+#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */
237+#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */
238+#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */
239+#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */
240+#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */
241+#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */
242+#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */
243+#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */
244+#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */
245+#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */
246+
247+#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */
248+#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */
249+#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */
250+
251+/* Section 4: Extended PHY Registers */
252+#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */
253+
254+#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */
255+#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */
256+
257+/* ################## SPI peripheral configuration ########################## */
258+
259+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
260+* Activated: CRC code is present inside driver
261+* Deactivated: CRC code cleaned from driver
262+*/
263+
264+#define USE_SPI_CRC 0U
265+
266+/* Includes ------------------------------------------------------------------*/
267+/**
268+ * @brief Include module's header file
269+ */
270+
271+#ifdef HAL_RCC_MODULE_ENABLED
272+ #include "stm32f4xx_hal_rcc.h"
273+#endif /* HAL_RCC_MODULE_ENABLED */
274+
275+#ifdef HAL_GPIO_MODULE_ENABLED
276+ #include "stm32f4xx_hal_gpio.h"
277+#endif /* HAL_GPIO_MODULE_ENABLED */
278+
279+#ifdef HAL_EXTI_MODULE_ENABLED
280+ #include "stm32f4xx_hal_exti.h"
281+#endif /* HAL_EXTI_MODULE_ENABLED */
282+
283+#ifdef HAL_DMA_MODULE_ENABLED
284+ #include "stm32f4xx_hal_dma.h"
285+#endif /* HAL_DMA_MODULE_ENABLED */
286+
287+#ifdef HAL_CORTEX_MODULE_ENABLED
288+ #include "stm32f4xx_hal_cortex.h"
289+#endif /* HAL_CORTEX_MODULE_ENABLED */
290+
291+#ifdef HAL_ADC_MODULE_ENABLED
292+ #include "stm32f4xx_hal_adc.h"
293+#endif /* HAL_ADC_MODULE_ENABLED */
294+
295+#ifdef HAL_CAN_MODULE_ENABLED
296+ #include "stm32f4xx_hal_can.h"
297+#endif /* HAL_CAN_MODULE_ENABLED */
298+
299+#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
300+ #include "stm32f4xx_hal_can_legacy.h"
301+#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
302+
303+#ifdef HAL_CRC_MODULE_ENABLED
304+ #include "stm32f4xx_hal_crc.h"
305+#endif /* HAL_CRC_MODULE_ENABLED */
306+
307+#ifdef HAL_CRYP_MODULE_ENABLED
308+ #include "stm32f4xx_hal_cryp.h"
309+#endif /* HAL_CRYP_MODULE_ENABLED */
310+
311+#ifdef HAL_DMA2D_MODULE_ENABLED
312+ #include "stm32f4xx_hal_dma2d.h"
313+#endif /* HAL_DMA2D_MODULE_ENABLED */
314+
315+#ifdef HAL_DAC_MODULE_ENABLED
316+ #include "stm32f4xx_hal_dac.h"
317+#endif /* HAL_DAC_MODULE_ENABLED */
318+
319+#ifdef HAL_DCMI_MODULE_ENABLED
320+ #include "stm32f4xx_hal_dcmi.h"
321+#endif /* HAL_DCMI_MODULE_ENABLED */
322+
323+#ifdef HAL_ETH_MODULE_ENABLED
324+ #include "stm32f4xx_hal_eth.h"
325+#endif /* HAL_ETH_MODULE_ENABLED */
326+
327+#ifdef HAL_FLASH_MODULE_ENABLED
328+ #include "stm32f4xx_hal_flash.h"
329+#endif /* HAL_FLASH_MODULE_ENABLED */
330+
331+#ifdef HAL_SRAM_MODULE_ENABLED
332+ #include "stm32f4xx_hal_sram.h"
333+#endif /* HAL_SRAM_MODULE_ENABLED */
334+
335+#ifdef HAL_NOR_MODULE_ENABLED
336+ #include "stm32f4xx_hal_nor.h"
337+#endif /* HAL_NOR_MODULE_ENABLED */
338+
339+#ifdef HAL_NAND_MODULE_ENABLED
340+ #include "stm32f4xx_hal_nand.h"
341+#endif /* HAL_NAND_MODULE_ENABLED */
342+
343+#ifdef HAL_PCCARD_MODULE_ENABLED
344+ #include "stm32f4xx_hal_pccard.h"
345+#endif /* HAL_PCCARD_MODULE_ENABLED */
346+
347+#ifdef HAL_SDRAM_MODULE_ENABLED
348+ #include "stm32f4xx_hal_sdram.h"
349+#endif /* HAL_SDRAM_MODULE_ENABLED */
350+
351+#ifdef HAL_HASH_MODULE_ENABLED
352+ #include "stm32f4xx_hal_hash.h"
353+#endif /* HAL_HASH_MODULE_ENABLED */
354+
355+#ifdef HAL_I2C_MODULE_ENABLED
356+ #include "stm32f4xx_hal_i2c.h"
357+#endif /* HAL_I2C_MODULE_ENABLED */
358+
359+#ifdef HAL_SMBUS_MODULE_ENABLED
360+ #include "stm32f4xx_hal_smbus.h"
361+#endif /* HAL_SMBUS_MODULE_ENABLED */
362+
363+#ifdef HAL_I2S_MODULE_ENABLED
364+ #include "stm32f4xx_hal_i2s.h"
365+#endif /* HAL_I2S_MODULE_ENABLED */
366+
367+#ifdef HAL_IWDG_MODULE_ENABLED
368+ #include "stm32f4xx_hal_iwdg.h"
369+#endif /* HAL_IWDG_MODULE_ENABLED */
370+
371+#ifdef HAL_LTDC_MODULE_ENABLED
372+ #include "stm32f4xx_hal_ltdc.h"
373+#endif /* HAL_LTDC_MODULE_ENABLED */
374+
375+#ifdef HAL_PWR_MODULE_ENABLED
376+ #include "stm32f4xx_hal_pwr.h"
377+#endif /* HAL_PWR_MODULE_ENABLED */
378+
379+#ifdef HAL_RNG_MODULE_ENABLED
380+ #include "stm32f4xx_hal_rng.h"
381+#endif /* HAL_RNG_MODULE_ENABLED */
382+
383+#ifdef HAL_RTC_MODULE_ENABLED
384+ #include "stm32f4xx_hal_rtc.h"
385+#endif /* HAL_RTC_MODULE_ENABLED */
386+
387+#ifdef HAL_SAI_MODULE_ENABLED
388+ #include "stm32f4xx_hal_sai.h"
389+#endif /* HAL_SAI_MODULE_ENABLED */
390+
391+#ifdef HAL_SD_MODULE_ENABLED
392+ #include "stm32f4xx_hal_sd.h"
393+#endif /* HAL_SD_MODULE_ENABLED */
394+
395+#ifdef HAL_SPI_MODULE_ENABLED
396+ #include "stm32f4xx_hal_spi.h"
397+#endif /* HAL_SPI_MODULE_ENABLED */
398+
399+#ifdef HAL_TIM_MODULE_ENABLED
400+ #include "stm32f4xx_hal_tim.h"
401+#endif /* HAL_TIM_MODULE_ENABLED */
402+
403+#ifdef HAL_UART_MODULE_ENABLED
404+ #include "stm32f4xx_hal_uart.h"
405+#endif /* HAL_UART_MODULE_ENABLED */
406+
407+#ifdef HAL_USART_MODULE_ENABLED
408+ #include "stm32f4xx_hal_usart.h"
409+#endif /* HAL_USART_MODULE_ENABLED */
410+
411+#ifdef HAL_IRDA_MODULE_ENABLED
412+ #include "stm32f4xx_hal_irda.h"
413+#endif /* HAL_IRDA_MODULE_ENABLED */
414+
415+#ifdef HAL_SMARTCARD_MODULE_ENABLED
416+ #include "stm32f4xx_hal_smartcard.h"
417+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
418+
419+#ifdef HAL_WWDG_MODULE_ENABLED
420+ #include "stm32f4xx_hal_wwdg.h"
421+#endif /* HAL_WWDG_MODULE_ENABLED */
422+
423+#ifdef HAL_PCD_MODULE_ENABLED
424+ #include "stm32f4xx_hal_pcd.h"
425+#endif /* HAL_PCD_MODULE_ENABLED */
426+
427+#ifdef HAL_HCD_MODULE_ENABLED
428+ #include "stm32f4xx_hal_hcd.h"
429+#endif /* HAL_HCD_MODULE_ENABLED */
430+
431+#ifdef HAL_DSI_MODULE_ENABLED
432+ #include "stm32f4xx_hal_dsi.h"
433+#endif /* HAL_DSI_MODULE_ENABLED */
434+
435+#ifdef HAL_QSPI_MODULE_ENABLED
436+ #include "stm32f4xx_hal_qspi.h"
437+#endif /* HAL_QSPI_MODULE_ENABLED */
438+
439+#ifdef HAL_CEC_MODULE_ENABLED
440+ #include "stm32f4xx_hal_cec.h"
441+#endif /* HAL_CEC_MODULE_ENABLED */
442+
443+#ifdef HAL_FMPI2C_MODULE_ENABLED
444+ #include "stm32f4xx_hal_fmpi2c.h"
445+#endif /* HAL_FMPI2C_MODULE_ENABLED */
446+
447+#ifdef HAL_SPDIFRX_MODULE_ENABLED
448+ #include "stm32f4xx_hal_spdifrx.h"
449+#endif /* HAL_SPDIFRX_MODULE_ENABLED */
450+
451+#ifdef HAL_DFSDM_MODULE_ENABLED
452+ #include "stm32f4xx_hal_dfsdm.h"
453+#endif /* HAL_DFSDM_MODULE_ENABLED */
454+
455+#ifdef HAL_LPTIM_MODULE_ENABLED
456+ #include "stm32f4xx_hal_lptim.h"
457+#endif /* HAL_LPTIM_MODULE_ENABLED */
458+
459+#ifdef HAL_MMC_MODULE_ENABLED
460+ #include "stm32f4xx_hal_mmc.h"
461+#endif /* HAL_MMC_MODULE_ENABLED */
462+
463+/* Exported macro ------------------------------------------------------------*/
464+#ifdef USE_FULL_ASSERT
465+/**
466+ * @brief The assert_param macro is used for function's parameters check.
467+ * @param expr If expr is false, it calls assert_failed function
468+ * which reports the name of the source file and the source
469+ * line number of the call that failed.
470+ * If expr is true, it returns no value.
471+ * @retval None
472+ */
473+ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
474+/* Exported functions ------------------------------------------------------- */
475+ void assert_failed(uint8_t* file, uint32_t line);
476+#else
477+ #define assert_param(expr) ((void)0U)
478+#endif /* USE_FULL_ASSERT */
479+
480+#ifdef __cplusplus
481+}
482+#endif
483+
484+#endif /* __STM32F4xx_HAL_CONF_H */
485+
486+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null
+++ b/gme_ws01/nuc-f429-blink/Core/Inc/stm32f4xx_it.h
@@ -0,0 +1,69 @@
1+/* USER CODE BEGIN Header */
2+/**
3+ ******************************************************************************
4+ * @file stm32f4xx_it.h
5+ * @brief This file contains the headers of the interrupt handlers.
6+ ******************************************************************************
7+ * @attention
8+ *
9+ * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
10+ * All rights reserved.</center></h2>
11+ *
12+ * This software component is licensed by ST under BSD 3-Clause license,
13+ * the "License"; You may not use this file except in compliance with the
14+ * License. You may obtain a copy of the License at:
15+ * opensource.org/licenses/BSD-3-Clause
16+ *
17+ ******************************************************************************
18+ */
19+/* USER CODE END Header */
20+
21+/* Define to prevent recursive inclusion -------------------------------------*/
22+#ifndef __STM32F4xx_IT_H
23+#define __STM32F4xx_IT_H
24+
25+#ifdef __cplusplus
26+ extern "C" {
27+#endif
28+
29+/* Private includes ----------------------------------------------------------*/
30+/* USER CODE BEGIN Includes */
31+
32+/* USER CODE END Includes */
33+
34+/* Exported types ------------------------------------------------------------*/
35+/* USER CODE BEGIN ET */
36+
37+/* USER CODE END ET */
38+
39+/* Exported constants --------------------------------------------------------*/
40+/* USER CODE BEGIN EC */
41+
42+/* USER CODE END EC */
43+
44+/* Exported macro ------------------------------------------------------------*/
45+/* USER CODE BEGIN EM */
46+
47+/* USER CODE END EM */
48+
49+/* Exported functions prototypes ---------------------------------------------*/
50+void NMI_Handler(void);
51+void HardFault_Handler(void);
52+void MemManage_Handler(void);
53+void BusFault_Handler(void);
54+void UsageFault_Handler(void);
55+void SVC_Handler(void);
56+void DebugMon_Handler(void);
57+void PendSV_Handler(void);
58+void SysTick_Handler(void);
59+/* USER CODE BEGIN EFP */
60+
61+/* USER CODE END EFP */
62+
63+#ifdef __cplusplus
64+}
65+#endif
66+
67+#endif /* __STM32F4xx_IT_H */
68+
69+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null
+++ b/gme_ws01/nuc-f429-blink/Core/Src/main.c
@@ -0,0 +1,304 @@
1+/* USER CODE BEGIN Header */
2+/**
3+ ******************************************************************************
4+ * @file : main.c
5+ * @brief : Main program body
6+ ******************************************************************************
7+ * @attention
8+ *
9+ * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
10+ * All rights reserved.</center></h2>
11+ *
12+ * This software component is licensed by ST under BSD 3-Clause license,
13+ * the "License"; You may not use this file except in compliance with the
14+ * License. You may obtain a copy of the License at:
15+ * opensource.org/licenses/BSD-3-Clause
16+ *
17+ ******************************************************************************
18+ */
19+/* USER CODE END Header */
20+/* Includes ------------------------------------------------------------------*/
21+#include "main.h"
22+
23+/* Private includes ----------------------------------------------------------*/
24+/* USER CODE BEGIN Includes */
25+
26+/* USER CODE END Includes */
27+
28+/* Private typedef -----------------------------------------------------------*/
29+/* USER CODE BEGIN PTD */
30+
31+/* USER CODE END PTD */
32+
33+/* Private define ------------------------------------------------------------*/
34+/* USER CODE BEGIN PD */
35+/* USER CODE END PD */
36+
37+/* Private macro -------------------------------------------------------------*/
38+/* USER CODE BEGIN PM */
39+
40+/* USER CODE END PM */
41+
42+/* Private variables ---------------------------------------------------------*/
43+
44+/* USER CODE BEGIN PV */
45+
46+/* USER CODE END PV */
47+
48+/* Private function prototypes -----------------------------------------------*/
49+void SystemClock_Config(void);
50+static void MX_GPIO_Init(void);
51+/* USER CODE BEGIN PFP */
52+
53+/* USER CODE END PFP */
54+
55+/* Private user code ---------------------------------------------------------*/
56+/* USER CODE BEGIN 0 */
57+
58+/* USER CODE END 0 */
59+
60+/**
61+ * @brief The application entry point.
62+ * @retval int
63+ */
64+int main(void)
65+{
66+ /* USER CODE BEGIN 1 */
67+
68+ /* USER CODE END 1 */
69+
70+ /* MCU Configuration--------------------------------------------------------*/
71+
72+ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
73+ HAL_Init();
74+
75+ /* USER CODE BEGIN Init */
76+
77+ /* USER CODE END Init */
78+
79+ /* Configure the system clock */
80+ SystemClock_Config();
81+
82+ /* USER CODE BEGIN SysInit */
83+
84+ /* USER CODE END SysInit */
85+
86+ /* Initialize all configured peripherals */
87+ MX_GPIO_Init();
88+ /* USER CODE BEGIN 2 */
89+
90+ /* USER CODE END 2 */
91+
92+ /* Infinite loop */
93+ /* USER CODE BEGIN WHILE */
94+ while (1)
95+ {
96+ /* USER CODE END WHILE */
97+
98+ /* USER CODE BEGIN 3 */
99+ }
100+ /* USER CODE END 3 */
101+}
102+
103+/**
104+ * @brief System Clock Configuration
105+ * @retval None
106+ */
107+void SystemClock_Config(void)
108+{
109+ RCC_OscInitTypeDef RCC_OscInitStruct = {0};
110+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
111+
112+ /** Configure the main internal regulator output voltage
113+ */
114+ __HAL_RCC_PWR_CLK_ENABLE();
115+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
116+ /** Initializes the RCC Oscillators according to the specified parameters
117+ * in the RCC_OscInitTypeDef structure.
118+ */
119+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
120+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
121+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
122+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
123+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
124+ RCC_OscInitStruct.PLL.PLLM = 8;
125+ RCC_OscInitStruct.PLL.PLLN = 168;
126+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
127+ RCC_OscInitStruct.PLL.PLLQ = 4;
128+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
129+ {
130+ Error_Handler();
131+ }
132+ /** Initializes the CPU, AHB and APB buses clocks
133+ */
134+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
135+ |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
136+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
137+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
138+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
139+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV4;
140+
141+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK)
142+ {
143+ Error_Handler();
144+ }
145+}
146+
147+/**
148+ * @brief GPIO Initialization Function
149+ * @param None
150+ * @retval None
151+ */
152+static void MX_GPIO_Init(void)
153+{
154+ LL_EXTI_InitTypeDef EXTI_InitStruct = {0};
155+ LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
156+
157+ /* GPIO Ports Clock Enable */
158+ LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOC);
159+ LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOH);
160+ LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOA);
161+ LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOB);
162+ LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOD);
163+ LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOG);
164+
165+ /**/
166+ LL_GPIO_ResetOutputPin(GPIOB, LD1_Pin|LD3_Pin|LD2_Pin);
167+
168+ /**/
169+ LL_GPIO_ResetOutputPin(USB_PowerSwitchOn_GPIO_Port, USB_PowerSwitchOn_Pin);
170+
171+ /**/
172+ LL_SYSCFG_SetEXTISource(LL_SYSCFG_EXTI_PORTC, LL_SYSCFG_EXTI_LINE13);
173+
174+ /**/
175+ EXTI_InitStruct.Line_0_31 = LL_EXTI_LINE_13;
176+ EXTI_InitStruct.LineCommand = ENABLE;
177+ EXTI_InitStruct.Mode = LL_EXTI_MODE_IT;
178+ EXTI_InitStruct.Trigger = LL_EXTI_TRIGGER_RISING;
179+ LL_EXTI_Init(&EXTI_InitStruct);
180+
181+ /**/
182+ LL_GPIO_SetPinPull(USER_Btn_GPIO_Port, USER_Btn_Pin, LL_GPIO_PULL_NO);
183+
184+ /**/
185+ LL_GPIO_SetPinMode(USER_Btn_GPIO_Port, USER_Btn_Pin, LL_GPIO_MODE_INPUT);
186+
187+ /**/
188+ GPIO_InitStruct.Pin = RMII_MDC_Pin|RMII_RXD0_Pin|RMII_RXD1_Pin;
189+ GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
190+ GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
191+ GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
192+ GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
193+ GPIO_InitStruct.Alternate = LL_GPIO_AF_11;
194+ LL_GPIO_Init(GPIOC, &GPIO_InitStruct);
195+
196+ /**/
197+ GPIO_InitStruct.Pin = RMII_REF_CLK_Pin|RMII_MDIO_Pin|RMII_CRS_DV_Pin;
198+ GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
199+ GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
200+ GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
201+ GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
202+ GPIO_InitStruct.Alternate = LL_GPIO_AF_11;
203+ LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
204+
205+ /**/
206+ GPIO_InitStruct.Pin = LD1_Pin|LD3_Pin|LD2_Pin;
207+ GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT;
208+ GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
209+ GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
210+ GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
211+ LL_GPIO_Init(GPIOB, &GPIO_InitStruct);
212+
213+ /**/
214+ GPIO_InitStruct.Pin = RMII_TXD1_Pin;
215+ GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
216+ GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
217+ GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
218+ GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
219+ GPIO_InitStruct.Alternate = LL_GPIO_AF_11;
220+ LL_GPIO_Init(RMII_TXD1_GPIO_Port, &GPIO_InitStruct);
221+
222+ /**/
223+ GPIO_InitStruct.Pin = STLK_RX_Pin|STLK_TX_Pin;
224+ GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
225+ GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
226+ GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
227+ GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
228+ GPIO_InitStruct.Alternate = LL_GPIO_AF_7;
229+ LL_GPIO_Init(GPIOD, &GPIO_InitStruct);
230+
231+ /**/
232+ GPIO_InitStruct.Pin = USB_PowerSwitchOn_Pin;
233+ GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT;
234+ GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
235+ GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
236+ GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
237+ LL_GPIO_Init(USB_PowerSwitchOn_GPIO_Port, &GPIO_InitStruct);
238+
239+ /**/
240+ GPIO_InitStruct.Pin = USB_OverCurrent_Pin;
241+ GPIO_InitStruct.Mode = LL_GPIO_MODE_INPUT;
242+ GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
243+ LL_GPIO_Init(USB_OverCurrent_GPIO_Port, &GPIO_InitStruct);
244+
245+ /**/
246+ GPIO_InitStruct.Pin = USB_SOF_Pin|USB_ID_Pin|USB_DM_Pin|USB_DP_Pin;
247+ GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
248+ GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
249+ GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
250+ GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
251+ GPIO_InitStruct.Alternate = LL_GPIO_AF_10;
252+ LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
253+
254+ /**/
255+ GPIO_InitStruct.Pin = USB_VBUS_Pin;
256+ GPIO_InitStruct.Mode = LL_GPIO_MODE_INPUT;
257+ GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
258+ LL_GPIO_Init(USB_VBUS_GPIO_Port, &GPIO_InitStruct);
259+
260+ /**/
261+ GPIO_InitStruct.Pin = RMII_TX_EN_Pin|RMII_TXD0_Pin;
262+ GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
263+ GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
264+ GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
265+ GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
266+ GPIO_InitStruct.Alternate = LL_GPIO_AF_11;
267+ LL_GPIO_Init(GPIOG, &GPIO_InitStruct);
268+
269+}
270+
271+/* USER CODE BEGIN 4 */
272+
273+/* USER CODE END 4 */
274+
275+/**
276+ * @brief This function is executed in case of error occurrence.
277+ * @retval None
278+ */
279+void Error_Handler(void)
280+{
281+ /* USER CODE BEGIN Error_Handler_Debug */
282+ /* User can add his own implementation to report the HAL error return state */
283+
284+ /* USER CODE END Error_Handler_Debug */
285+}
286+
287+#ifdef USE_FULL_ASSERT
288+/**
289+ * @brief Reports the name of the source file and the source line number
290+ * where the assert_param error has occurred.
291+ * @param file: pointer to the source file name
292+ * @param line: assert_param error line source number
293+ * @retval None
294+ */
295+void assert_failed(uint8_t *file, uint32_t line)
296+{
297+ /* USER CODE BEGIN 6 */
298+ /* User can add his own implementation to report the file name and line number,
299+ tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
300+ /* USER CODE END 6 */
301+}
302+#endif /* USE_FULL_ASSERT */
303+
304+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null
+++ b/gme_ws01/nuc-f429-blink/Core/Src/stm32f4xx_hal_msp.c
@@ -0,0 +1,84 @@
1+/* USER CODE BEGIN Header */
2+/**
3+ ******************************************************************************
4+ * File Name : stm32f4xx_hal_msp.c
5+ * Description : This file provides code for the MSP Initialization
6+ * and de-Initialization codes.
7+ ******************************************************************************
8+ * @attention
9+ *
10+ * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
11+ * All rights reserved.</center></h2>
12+ *
13+ * This software component is licensed by ST under BSD 3-Clause license,
14+ * the "License"; You may not use this file except in compliance with the
15+ * License. You may obtain a copy of the License at:
16+ * opensource.org/licenses/BSD-3-Clause
17+ *
18+ ******************************************************************************
19+ */
20+/* USER CODE END Header */
21+
22+/* Includes ------------------------------------------------------------------*/
23+#include "main.h"
24+/* USER CODE BEGIN Includes */
25+
26+/* USER CODE END Includes */
27+
28+/* Private typedef -----------------------------------------------------------*/
29+/* USER CODE BEGIN TD */
30+
31+/* USER CODE END TD */
32+
33+/* Private define ------------------------------------------------------------*/
34+/* USER CODE BEGIN Define */
35+
36+/* USER CODE END Define */
37+
38+/* Private macro -------------------------------------------------------------*/
39+/* USER CODE BEGIN Macro */
40+
41+/* USER CODE END Macro */
42+
43+/* Private variables ---------------------------------------------------------*/
44+/* USER CODE BEGIN PV */
45+
46+/* USER CODE END PV */
47+
48+/* Private function prototypes -----------------------------------------------*/
49+/* USER CODE BEGIN PFP */
50+
51+/* USER CODE END PFP */
52+
53+/* External functions --------------------------------------------------------*/
54+/* USER CODE BEGIN ExternalFunctions */
55+
56+/* USER CODE END ExternalFunctions */
57+
58+/* USER CODE BEGIN 0 */
59+
60+/* USER CODE END 0 */
61+/**
62+ * Initializes the Global MSP.
63+ */
64+void HAL_MspInit(void)
65+{
66+ /* USER CODE BEGIN MspInit 0 */
67+
68+ /* USER CODE END MspInit 0 */
69+
70+ __HAL_RCC_SYSCFG_CLK_ENABLE();
71+ __HAL_RCC_PWR_CLK_ENABLE();
72+
73+ /* System interrupt init*/
74+
75+ /* USER CODE BEGIN MspInit 1 */
76+
77+ /* USER CODE END MspInit 1 */
78+}
79+
80+/* USER CODE BEGIN 1 */
81+
82+/* USER CODE END 1 */
83+
84+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null
+++ b/gme_ws01/nuc-f429-blink/Core/Src/stm32f4xx_it.c
@@ -0,0 +1,203 @@
1+/* USER CODE BEGIN Header */
2+/**
3+ ******************************************************************************
4+ * @file stm32f4xx_it.c
5+ * @brief Interrupt Service Routines.
6+ ******************************************************************************
7+ * @attention
8+ *
9+ * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
10+ * All rights reserved.</center></h2>
11+ *
12+ * This software component is licensed by ST under BSD 3-Clause license,
13+ * the "License"; You may not use this file except in compliance with the
14+ * License. You may obtain a copy of the License at:
15+ * opensource.org/licenses/BSD-3-Clause
16+ *
17+ ******************************************************************************
18+ */
19+/* USER CODE END Header */
20+
21+/* Includes ------------------------------------------------------------------*/
22+#include "main.h"
23+#include "stm32f4xx_it.h"
24+/* Private includes ----------------------------------------------------------*/
25+/* USER CODE BEGIN Includes */
26+/* USER CODE END Includes */
27+
28+/* Private typedef -----------------------------------------------------------*/
29+/* USER CODE BEGIN TD */
30+
31+/* USER CODE END TD */
32+
33+/* Private define ------------------------------------------------------------*/
34+/* USER CODE BEGIN PD */
35+
36+/* USER CODE END PD */
37+
38+/* Private macro -------------------------------------------------------------*/
39+/* USER CODE BEGIN PM */
40+
41+/* USER CODE END PM */
42+
43+/* Private variables ---------------------------------------------------------*/
44+/* USER CODE BEGIN PV */
45+
46+/* USER CODE END PV */
47+
48+/* Private function prototypes -----------------------------------------------*/
49+/* USER CODE BEGIN PFP */
50+
51+/* USER CODE END PFP */
52+
53+/* Private user code ---------------------------------------------------------*/
54+/* USER CODE BEGIN 0 */
55+
56+/* USER CODE END 0 */
57+
58+/* External variables --------------------------------------------------------*/
59+
60+/* USER CODE BEGIN EV */
61+
62+/* USER CODE END EV */
63+
64+/******************************************************************************/
65+/* Cortex-M4 Processor Interruption and Exception Handlers */
66+/******************************************************************************/
67+/**
68+ * @brief This function handles Non maskable interrupt.
69+ */
70+void NMI_Handler(void)
71+{
72+ /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
73+
74+ /* USER CODE END NonMaskableInt_IRQn 0 */
75+ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
76+
77+ /* USER CODE END NonMaskableInt_IRQn 1 */
78+}
79+
80+/**
81+ * @brief This function handles Hard fault interrupt.
82+ */
83+void HardFault_Handler(void)
84+{
85+ /* USER CODE BEGIN HardFault_IRQn 0 */
86+
87+ /* USER CODE END HardFault_IRQn 0 */
88+ while (1)
89+ {
90+ /* USER CODE BEGIN W1_HardFault_IRQn 0 */
91+ /* USER CODE END W1_HardFault_IRQn 0 */
92+ }
93+}
94+
95+/**
96+ * @brief This function handles Memory management fault.
97+ */
98+void MemManage_Handler(void)
99+{
100+ /* USER CODE BEGIN MemoryManagement_IRQn 0 */
101+
102+ /* USER CODE END MemoryManagement_IRQn 0 */
103+ while (1)
104+ {
105+ /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
106+ /* USER CODE END W1_MemoryManagement_IRQn 0 */
107+ }
108+}
109+
110+/**
111+ * @brief This function handles Pre-fetch fault, memory access fault.
112+ */
113+void BusFault_Handler(void)
114+{
115+ /* USER CODE BEGIN BusFault_IRQn 0 */
116+
117+ /* USER CODE END BusFault_IRQn 0 */
118+ while (1)
119+ {
120+ /* USER CODE BEGIN W1_BusFault_IRQn 0 */
121+ /* USER CODE END W1_BusFault_IRQn 0 */
122+ }
123+}
124+
125+/**
126+ * @brief This function handles Undefined instruction or illegal state.
127+ */
128+void UsageFault_Handler(void)
129+{
130+ /* USER CODE BEGIN UsageFault_IRQn 0 */
131+
132+ /* USER CODE END UsageFault_IRQn 0 */
133+ while (1)
134+ {
135+ /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
136+ /* USER CODE END W1_UsageFault_IRQn 0 */
137+ }
138+}
139+
140+/**
141+ * @brief This function handles System service call via SWI instruction.
142+ */
143+void SVC_Handler(void)
144+{
145+ /* USER CODE BEGIN SVCall_IRQn 0 */
146+
147+ /* USER CODE END SVCall_IRQn 0 */
148+ /* USER CODE BEGIN SVCall_IRQn 1 */
149+
150+ /* USER CODE END SVCall_IRQn 1 */
151+}
152+
153+/**
154+ * @brief This function handles Debug monitor.
155+ */
156+void DebugMon_Handler(void)
157+{
158+ /* USER CODE BEGIN DebugMonitor_IRQn 0 */
159+
160+ /* USER CODE END DebugMonitor_IRQn 0 */
161+ /* USER CODE BEGIN DebugMonitor_IRQn 1 */
162+
163+ /* USER CODE END DebugMonitor_IRQn 1 */
164+}
165+
166+/**
167+ * @brief This function handles Pendable request for system service.
168+ */
169+void PendSV_Handler(void)
170+{
171+ /* USER CODE BEGIN PendSV_IRQn 0 */
172+
173+ /* USER CODE END PendSV_IRQn 0 */
174+ /* USER CODE BEGIN PendSV_IRQn 1 */
175+
176+ /* USER CODE END PendSV_IRQn 1 */
177+}
178+
179+/**
180+ * @brief This function handles System tick timer.
181+ */
182+void SysTick_Handler(void)
183+{
184+ /* USER CODE BEGIN SysTick_IRQn 0 */
185+
186+ /* USER CODE END SysTick_IRQn 0 */
187+ HAL_IncTick();
188+ /* USER CODE BEGIN SysTick_IRQn 1 */
189+
190+ /* USER CODE END SysTick_IRQn 1 */
191+}
192+
193+/******************************************************************************/
194+/* STM32F4xx Peripheral Interrupt Handlers */
195+/* Add here the Interrupt Handlers for the used peripherals. */
196+/* For the available peripheral interrupt handler names, */
197+/* please refer to the startup file (startup_stm32f4xx.s). */
198+/******************************************************************************/
199+
200+/* USER CODE BEGIN 1 */
201+
202+/* USER CODE END 1 */
203+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null
+++ b/gme_ws01/nuc-f429-blink/Core/Src/system_stm32f4xx.c
@@ -0,0 +1,727 @@
1+/**
2+ ******************************************************************************
3+ * @file system_stm32f4xx.c
4+ * @author MCD Application Team
5+ * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
6+ *
7+ * This file provides two functions and one global variable to be called from
8+ * user application:
9+ * - SystemInit(): This function is called at startup just after reset and
10+ * before branch to main program. This call is made inside
11+ * the "startup_stm32f4xx.s" file.
12+ *
13+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
14+ * by the user application to setup the SysTick
15+ * timer or configure other parameters.
16+ *
17+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
18+ * be called whenever the core clock is changed
19+ * during program execution.
20+ *
21+ *
22+ ******************************************************************************
23+ * @attention
24+ *
25+ * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
26+ * All rights reserved.</center></h2>
27+ *
28+ * This software component is licensed by ST under BSD 3-Clause license,
29+ * the "License"; You may not use this file except in compliance with the
30+ * License. You may obtain a copy of the License at:
31+ * opensource.org/licenses/BSD-3-Clause
32+ *
33+ ******************************************************************************
34+ */
35+
36+/** @addtogroup CMSIS
37+ * @{
38+ */
39+
40+/** @addtogroup stm32f4xx_system
41+ * @{
42+ */
43+
44+/** @addtogroup STM32F4xx_System_Private_Includes
45+ * @{
46+ */
47+
48+
49+#include "stm32f4xx.h"
50+
51+#if !defined (HSE_VALUE)
52+ #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
53+#endif /* HSE_VALUE */
54+
55+#if !defined (HSI_VALUE)
56+ #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
57+#endif /* HSI_VALUE */
58+
59+/**
60+ * @}
61+ */
62+
63+/** @addtogroup STM32F4xx_System_Private_TypesDefinitions
64+ * @{
65+ */
66+
67+/**
68+ * @}
69+ */
70+
71+/** @addtogroup STM32F4xx_System_Private_Defines
72+ * @{
73+ */
74+
75+/************************* Miscellaneous Configuration ************************/
76+/*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */
77+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
78+ || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
79+ || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
80+/* #define DATA_IN_ExtSRAM */
81+#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\
82+ STM32F412Zx || STM32F412Vx */
83+
84+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
85+ || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
86+/* #define DATA_IN_ExtSDRAM */
87+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\
88+ STM32F479xx */
89+
90+/*!< Uncomment the following line if you need to relocate your vector Table in
91+ Internal SRAM. */
92+/* #define VECT_TAB_SRAM */
93+#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
94+ This value must be a multiple of 0x200. */
95+/******************************************************************************/
96+
97+/**
98+ * @}
99+ */
100+
101+/** @addtogroup STM32F4xx_System_Private_Macros
102+ * @{
103+ */
104+
105+/**
106+ * @}
107+ */
108+
109+/** @addtogroup STM32F4xx_System_Private_Variables
110+ * @{
111+ */
112+ /* This variable is updated in three ways:
113+ 1) by calling CMSIS function SystemCoreClockUpdate()
114+ 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
115+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
116+ Note: If you use this function to configure the system clock; then there
117+ is no need to call the 2 first functions listed above, since SystemCoreClock
118+ variable is updated automatically.
119+ */
120+uint32_t SystemCoreClock = 16000000;
121+const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
122+const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
123+/**
124+ * @}
125+ */
126+
127+/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
128+ * @{
129+ */
130+
131+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
132+ static void SystemInit_ExtMemCtl(void);
133+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
134+
135+/**
136+ * @}
137+ */
138+
139+/** @addtogroup STM32F4xx_System_Private_Functions
140+ * @{
141+ */
142+
143+/**
144+ * @brief Setup the microcontroller system
145+ * Initialize the FPU setting, vector table location and External memory
146+ * configuration.
147+ * @param None
148+ * @retval None
149+ */
150+void SystemInit(void)
151+{
152+ /* FPU settings ------------------------------------------------------------*/
153+ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
154+ SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
155+ #endif
156+
157+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
158+ SystemInit_ExtMemCtl();
159+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
160+
161+ /* Configure the Vector Table location add offset address ------------------*/
162+#ifdef VECT_TAB_SRAM
163+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
164+#else
165+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
166+#endif
167+}
168+
169+/**
170+ * @brief Update SystemCoreClock variable according to Clock Register Values.
171+ * The SystemCoreClock variable contains the core clock (HCLK), it can
172+ * be used by the user application to setup the SysTick timer or configure
173+ * other parameters.
174+ *
175+ * @note Each time the core clock (HCLK) changes, this function must be called
176+ * to update SystemCoreClock variable value. Otherwise, any configuration
177+ * based on this variable will be incorrect.
178+ *
179+ * @note - The system frequency computed by this function is not the real
180+ * frequency in the chip. It is calculated based on the predefined
181+ * constant and the selected clock source:
182+ *
183+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
184+ *
185+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
186+ *
187+ * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
188+ * or HSI_VALUE(*) multiplied/divided by the PLL factors.
189+ *
190+ * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
191+ * 16 MHz) but the real value may vary depending on the variations
192+ * in voltage and temperature.
193+ *
194+ * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
195+ * depends on the application requirements), user has to ensure that HSE_VALUE
196+ * is same as the real frequency of the crystal used. Otherwise, this function
197+ * may have wrong result.
198+ *
199+ * - The result of this function could be not correct when using fractional
200+ * value for HSE crystal.
201+ *
202+ * @param None
203+ * @retval None
204+ */
205+void SystemCoreClockUpdate(void)
206+{
207+ uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
208+
209+ /* Get SYSCLK source -------------------------------------------------------*/
210+ tmp = RCC->CFGR & RCC_CFGR_SWS;
211+
212+ switch (tmp)
213+ {
214+ case 0x00: /* HSI used as system clock source */
215+ SystemCoreClock = HSI_VALUE;
216+ break;
217+ case 0x04: /* HSE used as system clock source */
218+ SystemCoreClock = HSE_VALUE;
219+ break;
220+ case 0x08: /* PLL used as system clock source */
221+
222+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
223+ SYSCLK = PLL_VCO / PLL_P
224+ */
225+ pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
226+ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
227+
228+ if (pllsource != 0)
229+ {
230+ /* HSE used as PLL clock source */
231+ pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
232+ }
233+ else
234+ {
235+ /* HSI used as PLL clock source */
236+ pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
237+ }
238+
239+ pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
240+ SystemCoreClock = pllvco/pllp;
241+ break;
242+ default:
243+ SystemCoreClock = HSI_VALUE;
244+ break;
245+ }
246+ /* Compute HCLK frequency --------------------------------------------------*/
247+ /* Get HCLK prescaler */
248+ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
249+ /* HCLK frequency */
250+ SystemCoreClock >>= tmp;
251+}
252+
253+#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM)
254+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
255+ || defined(STM32F469xx) || defined(STM32F479xx)
256+/**
257+ * @brief Setup the external memory controller.
258+ * Called in startup_stm32f4xx.s before jump to main.
259+ * This function configures the external memories (SRAM/SDRAM)
260+ * This SRAM/SDRAM will be used as program data memory (including heap and stack).
261+ * @param None
262+ * @retval None
263+ */
264+void SystemInit_ExtMemCtl(void)
265+{
266+ __IO uint32_t tmp = 0x00;
267+
268+ register uint32_t tmpreg = 0, timeout = 0xFFFF;
269+ register __IO uint32_t index;
270+
271+ /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */
272+ RCC->AHB1ENR |= 0x000001F8;
273+
274+ /* Delay after an RCC peripheral clock enabling */
275+ tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
276+
277+ /* Connect PDx pins to FMC Alternate function */
278+ GPIOD->AFR[0] = 0x00CCC0CC;
279+ GPIOD->AFR[1] = 0xCCCCCCCC;
280+ /* Configure PDx pins in Alternate function mode */
281+ GPIOD->MODER = 0xAAAA0A8A;
282+ /* Configure PDx pins speed to 100 MHz */
283+ GPIOD->OSPEEDR = 0xFFFF0FCF;
284+ /* Configure PDx pins Output type to push-pull */
285+ GPIOD->OTYPER = 0x00000000;
286+ /* No pull-up, pull-down for PDx pins */
287+ GPIOD->PUPDR = 0x00000000;
288+
289+ /* Connect PEx pins to FMC Alternate function */
290+ GPIOE->AFR[0] = 0xC00CC0CC;
291+ GPIOE->AFR[1] = 0xCCCCCCCC;
292+ /* Configure PEx pins in Alternate function mode */
293+ GPIOE->MODER = 0xAAAA828A;
294+ /* Configure PEx pins speed to 100 MHz */
295+ GPIOE->OSPEEDR = 0xFFFFC3CF;
296+ /* Configure PEx pins Output type to push-pull */
297+ GPIOE->OTYPER = 0x00000000;
298+ /* No pull-up, pull-down for PEx pins */
299+ GPIOE->PUPDR = 0x00000000;
300+
301+ /* Connect PFx pins to FMC Alternate function */
302+ GPIOF->AFR[0] = 0xCCCCCCCC;
303+ GPIOF->AFR[1] = 0xCCCCCCCC;
304+ /* Configure PFx pins in Alternate function mode */
305+ GPIOF->MODER = 0xAA800AAA;
306+ /* Configure PFx pins speed to 50 MHz */
307+ GPIOF->OSPEEDR = 0xAA800AAA;
308+ /* Configure PFx pins Output type to push-pull */
309+ GPIOF->OTYPER = 0x00000000;
310+ /* No pull-up, pull-down for PFx pins */
311+ GPIOF->PUPDR = 0x00000000;
312+
313+ /* Connect PGx pins to FMC Alternate function */
314+ GPIOG->AFR[0] = 0xCCCCCCCC;
315+ GPIOG->AFR[1] = 0xCCCCCCCC;
316+ /* Configure PGx pins in Alternate function mode */
317+ GPIOG->MODER = 0xAAAAAAAA;
318+ /* Configure PGx pins speed to 50 MHz */
319+ GPIOG->OSPEEDR = 0xAAAAAAAA;
320+ /* Configure PGx pins Output type to push-pull */
321+ GPIOG->OTYPER = 0x00000000;
322+ /* No pull-up, pull-down for PGx pins */
323+ GPIOG->PUPDR = 0x00000000;
324+
325+ /* Connect PHx pins to FMC Alternate function */
326+ GPIOH->AFR[0] = 0x00C0CC00;
327+ GPIOH->AFR[1] = 0xCCCCCCCC;
328+ /* Configure PHx pins in Alternate function mode */
329+ GPIOH->MODER = 0xAAAA08A0;
330+ /* Configure PHx pins speed to 50 MHz */
331+ GPIOH->OSPEEDR = 0xAAAA08A0;
332+ /* Configure PHx pins Output type to push-pull */
333+ GPIOH->OTYPER = 0x00000000;
334+ /* No pull-up, pull-down for PHx pins */
335+ GPIOH->PUPDR = 0x00000000;
336+
337+ /* Connect PIx pins to FMC Alternate function */
338+ GPIOI->AFR[0] = 0xCCCCCCCC;
339+ GPIOI->AFR[1] = 0x00000CC0;
340+ /* Configure PIx pins in Alternate function mode */
341+ GPIOI->MODER = 0x0028AAAA;
342+ /* Configure PIx pins speed to 50 MHz */
343+ GPIOI->OSPEEDR = 0x0028AAAA;
344+ /* Configure PIx pins Output type to push-pull */
345+ GPIOI->OTYPER = 0x00000000;
346+ /* No pull-up, pull-down for PIx pins */
347+ GPIOI->PUPDR = 0x00000000;
348+
349+/*-- FMC Configuration -------------------------------------------------------*/
350+ /* Enable the FMC interface clock */
351+ RCC->AHB3ENR |= 0x00000001;
352+ /* Delay after an RCC peripheral clock enabling */
353+ tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
354+
355+ FMC_Bank5_6->SDCR[0] = 0x000019E4;
356+ FMC_Bank5_6->SDTR[0] = 0x01115351;
357+
358+ /* SDRAM initialization sequence */
359+ /* Clock enable command */
360+ FMC_Bank5_6->SDCMR = 0x00000011;
361+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
362+ while((tmpreg != 0) && (timeout-- > 0))
363+ {
364+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
365+ }
366+
367+ /* Delay */
368+ for (index = 0; index<1000; index++);
369+
370+ /* PALL command */
371+ FMC_Bank5_6->SDCMR = 0x00000012;
372+ timeout = 0xFFFF;
373+ while((tmpreg != 0) && (timeout-- > 0))
374+ {
375+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
376+ }
377+
378+ /* Auto refresh command */
379+ FMC_Bank5_6->SDCMR = 0x00000073;
380+ timeout = 0xFFFF;
381+ while((tmpreg != 0) && (timeout-- > 0))
382+ {
383+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
384+ }
385+
386+ /* MRD register program */
387+ FMC_Bank5_6->SDCMR = 0x00046014;
388+ timeout = 0xFFFF;
389+ while((tmpreg != 0) && (timeout-- > 0))
390+ {
391+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
392+ }
393+
394+ /* Set refresh count */
395+ tmpreg = FMC_Bank5_6->SDRTR;
396+ FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
397+
398+ /* Disable write protection */
399+ tmpreg = FMC_Bank5_6->SDCR[0];
400+ FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
401+
402+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
403+ /* Configure and enable Bank1_SRAM2 */
404+ FMC_Bank1->BTCR[2] = 0x00001011;
405+ FMC_Bank1->BTCR[3] = 0x00000201;
406+ FMC_Bank1E->BWTR[2] = 0x0fffffff;
407+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
408+#if defined(STM32F469xx) || defined(STM32F479xx)
409+ /* Configure and enable Bank1_SRAM2 */
410+ FMC_Bank1->BTCR[2] = 0x00001091;
411+ FMC_Bank1->BTCR[3] = 0x00110212;
412+ FMC_Bank1E->BWTR[2] = 0x0fffffff;
413+#endif /* STM32F469xx || STM32F479xx */
414+
415+ (void)(tmp);
416+}
417+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
418+#elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
419+/**
420+ * @brief Setup the external memory controller.
421+ * Called in startup_stm32f4xx.s before jump to main.
422+ * This function configures the external memories (SRAM/SDRAM)
423+ * This SRAM/SDRAM will be used as program data memory (including heap and stack).
424+ * @param None
425+ * @retval None
426+ */
427+void SystemInit_ExtMemCtl(void)
428+{
429+ __IO uint32_t tmp = 0x00;
430+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
431+ || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
432+#if defined (DATA_IN_ExtSDRAM)
433+ register uint32_t tmpreg = 0, timeout = 0xFFFF;
434+ register __IO uint32_t index;
435+
436+#if defined(STM32F446xx)
437+ /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface
438+ clock */
439+ RCC->AHB1ENR |= 0x0000007D;
440+#else
441+ /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
442+ clock */
443+ RCC->AHB1ENR |= 0x000001F8;
444+#endif /* STM32F446xx */
445+ /* Delay after an RCC peripheral clock enabling */
446+ tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
447+
448+#if defined(STM32F446xx)
449+ /* Connect PAx pins to FMC Alternate function */
450+ GPIOA->AFR[0] |= 0xC0000000;
451+ GPIOA->AFR[1] |= 0x00000000;
452+ /* Configure PDx pins in Alternate function mode */
453+ GPIOA->MODER |= 0x00008000;
454+ /* Configure PDx pins speed to 50 MHz */
455+ GPIOA->OSPEEDR |= 0x00008000;
456+ /* Configure PDx pins Output type to push-pull */
457+ GPIOA->OTYPER |= 0x00000000;
458+ /* No pull-up, pull-down for PDx pins */
459+ GPIOA->PUPDR |= 0x00000000;
460+
461+ /* Connect PCx pins to FMC Alternate function */
462+ GPIOC->AFR[0] |= 0x00CC0000;
463+ GPIOC->AFR[1] |= 0x00000000;
464+ /* Configure PDx pins in Alternate function mode */
465+ GPIOC->MODER |= 0x00000A00;
466+ /* Configure PDx pins speed to 50 MHz */
467+ GPIOC->OSPEEDR |= 0x00000A00;
468+ /* Configure PDx pins Output type to push-pull */
469+ GPIOC->OTYPER |= 0x00000000;
470+ /* No pull-up, pull-down for PDx pins */
471+ GPIOC->PUPDR |= 0x00000000;
472+#endif /* STM32F446xx */
473+
474+ /* Connect PDx pins to FMC Alternate function */
475+ GPIOD->AFR[0] = 0x000000CC;
476+ GPIOD->AFR[1] = 0xCC000CCC;
477+ /* Configure PDx pins in Alternate function mode */
478+ GPIOD->MODER = 0xA02A000A;
479+ /* Configure PDx pins speed to 50 MHz */
480+ GPIOD->OSPEEDR = 0xA02A000A;
481+ /* Configure PDx pins Output type to push-pull */
482+ GPIOD->OTYPER = 0x00000000;
483+ /* No pull-up, pull-down for PDx pins */
484+ GPIOD->PUPDR = 0x00000000;
485+
486+ /* Connect PEx pins to FMC Alternate function */
487+ GPIOE->AFR[0] = 0xC00000CC;
488+ GPIOE->AFR[1] = 0xCCCCCCCC;
489+ /* Configure PEx pins in Alternate function mode */
490+ GPIOE->MODER = 0xAAAA800A;
491+ /* Configure PEx pins speed to 50 MHz */
492+ GPIOE->OSPEEDR = 0xAAAA800A;
493+ /* Configure PEx pins Output type to push-pull */
494+ GPIOE->OTYPER = 0x00000000;
495+ /* No pull-up, pull-down for PEx pins */
496+ GPIOE->PUPDR = 0x00000000;
497+
498+ /* Connect PFx pins to FMC Alternate function */
499+ GPIOF->AFR[0] = 0xCCCCCCCC;
500+ GPIOF->AFR[1] = 0xCCCCCCCC;
501+ /* Configure PFx pins in Alternate function mode */
502+ GPIOF->MODER = 0xAA800AAA;
503+ /* Configure PFx pins speed to 50 MHz */
504+ GPIOF->OSPEEDR = 0xAA800AAA;
505+ /* Configure PFx pins Output type to push-pull */
506+ GPIOF->OTYPER = 0x00000000;
507+ /* No pull-up, pull-down for PFx pins */
508+ GPIOF->PUPDR = 0x00000000;
509+
510+ /* Connect PGx pins to FMC Alternate function */
511+ GPIOG->AFR[0] = 0xCCCCCCCC;
512+ GPIOG->AFR[1] = 0xCCCCCCCC;
513+ /* Configure PGx pins in Alternate function mode */
514+ GPIOG->MODER = 0xAAAAAAAA;
515+ /* Configure PGx pins speed to 50 MHz */
516+ GPIOG->OSPEEDR = 0xAAAAAAAA;
517+ /* Configure PGx pins Output type to push-pull */
518+ GPIOG->OTYPER = 0x00000000;
519+ /* No pull-up, pull-down for PGx pins */
520+ GPIOG->PUPDR = 0x00000000;
521+
522+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
523+ || defined(STM32F469xx) || defined(STM32F479xx)
524+ /* Connect PHx pins to FMC Alternate function */
525+ GPIOH->AFR[0] = 0x00C0CC00;
526+ GPIOH->AFR[1] = 0xCCCCCCCC;
527+ /* Configure PHx pins in Alternate function mode */
528+ GPIOH->MODER = 0xAAAA08A0;
529+ /* Configure PHx pins speed to 50 MHz */
530+ GPIOH->OSPEEDR = 0xAAAA08A0;
531+ /* Configure PHx pins Output type to push-pull */
532+ GPIOH->OTYPER = 0x00000000;
533+ /* No pull-up, pull-down for PHx pins */
534+ GPIOH->PUPDR = 0x00000000;
535+
536+ /* Connect PIx pins to FMC Alternate function */
537+ GPIOI->AFR[0] = 0xCCCCCCCC;
538+ GPIOI->AFR[1] = 0x00000CC0;
539+ /* Configure PIx pins in Alternate function mode */
540+ GPIOI->MODER = 0x0028AAAA;
541+ /* Configure PIx pins speed to 50 MHz */
542+ GPIOI->OSPEEDR = 0x0028AAAA;
543+ /* Configure PIx pins Output type to push-pull */
544+ GPIOI->OTYPER = 0x00000000;
545+ /* No pull-up, pull-down for PIx pins */
546+ GPIOI->PUPDR = 0x00000000;
547+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
548+
549+/*-- FMC Configuration -------------------------------------------------------*/
550+ /* Enable the FMC interface clock */
551+ RCC->AHB3ENR |= 0x00000001;
552+ /* Delay after an RCC peripheral clock enabling */
553+ tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
554+
555+ /* Configure and enable SDRAM bank1 */
556+#if defined(STM32F446xx)
557+ FMC_Bank5_6->SDCR[0] = 0x00001954;
558+#else
559+ FMC_Bank5_6->SDCR[0] = 0x000019E4;
560+#endif /* STM32F446xx */
561+ FMC_Bank5_6->SDTR[0] = 0x01115351;
562+
563+ /* SDRAM initialization sequence */
564+ /* Clock enable command */
565+ FMC_Bank5_6->SDCMR = 0x00000011;
566+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
567+ while((tmpreg != 0) && (timeout-- > 0))
568+ {
569+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
570+ }
571+
572+ /* Delay */
573+ for (index = 0; index<1000; index++);
574+
575+ /* PALL command */
576+ FMC_Bank5_6->SDCMR = 0x00000012;
577+ timeout = 0xFFFF;
578+ while((tmpreg != 0) && (timeout-- > 0))
579+ {
580+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
581+ }
582+
583+ /* Auto refresh command */
584+#if defined(STM32F446xx)
585+ FMC_Bank5_6->SDCMR = 0x000000F3;
586+#else
587+ FMC_Bank5_6->SDCMR = 0x00000073;
588+#endif /* STM32F446xx */
589+ timeout = 0xFFFF;
590+ while((tmpreg != 0) && (timeout-- > 0))
591+ {
592+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
593+ }
594+
595+ /* MRD register program */
596+#if defined(STM32F446xx)
597+ FMC_Bank5_6->SDCMR = 0x00044014;
598+#else
599+ FMC_Bank5_6->SDCMR = 0x00046014;
600+#endif /* STM32F446xx */
601+ timeout = 0xFFFF;
602+ while((tmpreg != 0) && (timeout-- > 0))
603+ {
604+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
605+ }
606+
607+ /* Set refresh count */
608+ tmpreg = FMC_Bank5_6->SDRTR;
609+#if defined(STM32F446xx)
610+ FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1));
611+#else
612+ FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
613+#endif /* STM32F446xx */
614+
615+ /* Disable write protection */
616+ tmpreg = FMC_Bank5_6->SDCR[0];
617+ FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
618+#endif /* DATA_IN_ExtSDRAM */
619+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
620+
621+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
622+ || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
623+ || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
624+
625+#if defined(DATA_IN_ExtSRAM)
626+/*-- GPIOs Configuration -----------------------------------------------------*/
627+ /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
628+ RCC->AHB1ENR |= 0x00000078;
629+ /* Delay after an RCC peripheral clock enabling */
630+ tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);
631+
632+ /* Connect PDx pins to FMC Alternate function */
633+ GPIOD->AFR[0] = 0x00CCC0CC;
634+ GPIOD->AFR[1] = 0xCCCCCCCC;
635+ /* Configure PDx pins in Alternate function mode */
636+ GPIOD->MODER = 0xAAAA0A8A;
637+ /* Configure PDx pins speed to 100 MHz */
638+ GPIOD->OSPEEDR = 0xFFFF0FCF;
639+ /* Configure PDx pins Output type to push-pull */
640+ GPIOD->OTYPER = 0x00000000;
641+ /* No pull-up, pull-down for PDx pins */
642+ GPIOD->PUPDR = 0x00000000;
643+
644+ /* Connect PEx pins to FMC Alternate function */
645+ GPIOE->AFR[0] = 0xC00CC0CC;
646+ GPIOE->AFR[1] = 0xCCCCCCCC;
647+ /* Configure PEx pins in Alternate function mode */
648+ GPIOE->MODER = 0xAAAA828A;
649+ /* Configure PEx pins speed to 100 MHz */
650+ GPIOE->OSPEEDR = 0xFFFFC3CF;
651+ /* Configure PEx pins Output type to push-pull */
652+ GPIOE->OTYPER = 0x00000000;
653+ /* No pull-up, pull-down for PEx pins */
654+ GPIOE->PUPDR = 0x00000000;
655+
656+ /* Connect PFx pins to FMC Alternate function */
657+ GPIOF->AFR[0] = 0x00CCCCCC;
658+ GPIOF->AFR[1] = 0xCCCC0000;
659+ /* Configure PFx pins in Alternate function mode */
660+ GPIOF->MODER = 0xAA000AAA;
661+ /* Configure PFx pins speed to 100 MHz */
662+ GPIOF->OSPEEDR = 0xFF000FFF;
663+ /* Configure PFx pins Output type to push-pull */
664+ GPIOF->OTYPER = 0x00000000;
665+ /* No pull-up, pull-down for PFx pins */
666+ GPIOF->PUPDR = 0x00000000;
667+
668+ /* Connect PGx pins to FMC Alternate function */
669+ GPIOG->AFR[0] = 0x00CCCCCC;
670+ GPIOG->AFR[1] = 0x000000C0;
671+ /* Configure PGx pins in Alternate function mode */
672+ GPIOG->MODER = 0x00085AAA;
673+ /* Configure PGx pins speed to 100 MHz */
674+ GPIOG->OSPEEDR = 0x000CAFFF;
675+ /* Configure PGx pins Output type to push-pull */
676+ GPIOG->OTYPER = 0x00000000;
677+ /* No pull-up, pull-down for PGx pins */
678+ GPIOG->PUPDR = 0x00000000;
679+
680+/*-- FMC/FSMC Configuration --------------------------------------------------*/
681+ /* Enable the FMC/FSMC interface clock */
682+ RCC->AHB3ENR |= 0x00000001;
683+
684+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
685+ /* Delay after an RCC peripheral clock enabling */
686+ tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
687+ /* Configure and enable Bank1_SRAM2 */
688+ FMC_Bank1->BTCR[2] = 0x00001011;
689+ FMC_Bank1->BTCR[3] = 0x00000201;
690+ FMC_Bank1E->BWTR[2] = 0x0fffffff;
691+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
692+#if defined(STM32F469xx) || defined(STM32F479xx)
693+ /* Delay after an RCC peripheral clock enabling */
694+ tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
695+ /* Configure and enable Bank1_SRAM2 */
696+ FMC_Bank1->BTCR[2] = 0x00001091;
697+ FMC_Bank1->BTCR[3] = 0x00110212;
698+ FMC_Bank1E->BWTR[2] = 0x0fffffff;
699+#endif /* STM32F469xx || STM32F479xx */
700+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\
701+ || defined(STM32F412Zx) || defined(STM32F412Vx)
702+ /* Delay after an RCC peripheral clock enabling */
703+ tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);
704+ /* Configure and enable Bank1_SRAM2 */
705+ FSMC_Bank1->BTCR[2] = 0x00001011;
706+ FSMC_Bank1->BTCR[3] = 0x00000201;
707+ FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
708+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */
709+
710+#endif /* DATA_IN_ExtSRAM */
711+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
712+ STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx */
713+ (void)(tmp);
714+}
715+#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
716+/**
717+ * @}
718+ */
719+
720+/**
721+ * @}
722+ */
723+
724+/**
725+ * @}
726+ */
727+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null
+++ b/gme_ws01/nuc-f429-blink/Makefile
@@ -0,0 +1,196 @@
1+##########################################################################################################################
2+# File automatically-generated by tool: [projectgenerator] version: [3.10.0-B14] date: [Sat Nov 07 17:24:39 JST 2020]
3+##########################################################################################################################
4+
5+# ------------------------------------------------
6+# Generic Makefile (based on gcc)
7+#
8+# ChangeLog :
9+# 2017-02-10 - Several enhancements + project update mode
10+# 2015-07-22 - first version
11+# ------------------------------------------------
12+
13+######################################
14+# target
15+######################################
16+TARGET = nuc-f429-blink
17+
18+
19+######################################
20+# building variables
21+######################################
22+# debug build?
23+DEBUG = 1
24+# optimization
25+OPT = -Og
26+
27+
28+#######################################
29+# paths
30+#######################################
31+# Build path
32+BUILD_DIR = build
33+
34+######################################
35+# source
36+######################################
37+# C sources
38+C_SOURCES = \
39+Core/Src/main.c \
40+Core/Src/stm32f4xx_it.c \
41+Core/Src/stm32f4xx_hal_msp.c \
42+C:/Dev0/CubeRepo/STM32Cube_FW_F4_V1.25.1/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_gpio.c \
43+C:/Dev0/CubeRepo/STM32Cube_FW_F4_V1.25.1/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c \
44+C:/Dev0/CubeRepo/STM32Cube_FW_F4_V1.25.1/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c \
45+C:/Dev0/CubeRepo/STM32Cube_FW_F4_V1.25.1/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c \
46+C:/Dev0/CubeRepo/STM32Cube_FW_F4_V1.25.1/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c \
47+C:/Dev0/CubeRepo/STM32Cube_FW_F4_V1.25.1/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c \
48+C:/Dev0/CubeRepo/STM32Cube_FW_F4_V1.25.1/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c \
49+C:/Dev0/CubeRepo/STM32Cube_FW_F4_V1.25.1/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c \
50+C:/Dev0/CubeRepo/STM32Cube_FW_F4_V1.25.1/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c \
51+C:/Dev0/CubeRepo/STM32Cube_FW_F4_V1.25.1/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c \
52+C:/Dev0/CubeRepo/STM32Cube_FW_F4_V1.25.1/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c \
53+C:/Dev0/CubeRepo/STM32Cube_FW_F4_V1.25.1/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c \
54+C:/Dev0/CubeRepo/STM32Cube_FW_F4_V1.25.1/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c \
55+C:/Dev0/CubeRepo/STM32Cube_FW_F4_V1.25.1/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c \
56+C:/Dev0/CubeRepo/STM32Cube_FW_F4_V1.25.1/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c \
57+C:/Dev0/CubeRepo/STM32Cube_FW_F4_V1.25.1/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c \
58+C:/Dev0/CubeRepo/STM32Cube_FW_F4_V1.25.1/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_rcc.c \
59+C:/Dev0/CubeRepo/STM32Cube_FW_F4_V1.25.1/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_utils.c \
60+C:/Dev0/CubeRepo/STM32Cube_FW_F4_V1.25.1/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_exti.c \
61+Core/Src/system_stm32f4xx.c
62+
63+# ASM sources
64+ASM_SOURCES = \
65+startup_stm32f429xx.s
66+
67+
68+#######################################
69+# binaries
70+#######################################
71+PREFIX = arm-none-eabi-
72+# The gcc compiler bin path can be either defined in make command via GCC_PATH variable (> make GCC_PATH=xxx)
73+# either it can be added to the PATH environment variable.
74+ifdef GCC_PATH
75+CC = $(GCC_PATH)/$(PREFIX)gcc
76+AS = $(GCC_PATH)/$(PREFIX)gcc -x assembler-with-cpp
77+CP = $(GCC_PATH)/$(PREFIX)objcopy
78+SZ = $(GCC_PATH)/$(PREFIX)size
79+else
80+CC = $(PREFIX)gcc
81+AS = $(PREFIX)gcc -x assembler-with-cpp
82+CP = $(PREFIX)objcopy
83+SZ = $(PREFIX)size
84+endif
85+HEX = $(CP) -O ihex
86+BIN = $(CP) -O binary -S
87+
88+#######################################
89+# CFLAGS
90+#######################################
91+# cpu
92+CPU = -mcpu=cortex-m4
93+
94+# fpu
95+FPU = -mfpu=fpv4-sp-d16
96+
97+# float-abi
98+FLOAT-ABI = -mfloat-abi=hard
99+
100+# mcu
101+MCU = $(CPU) -mthumb $(FPU) $(FLOAT-ABI)
102+
103+# macros for gcc
104+# AS defines
105+AS_DEFS =
106+
107+# C defines
108+C_DEFS = \
109+-DUSE_FULL_LL_DRIVER \
110+-DUSE_HAL_DRIVER \
111+-DSTM32F429xx
112+
113+
114+# AS includes
115+AS_INCLUDES =
116+
117+# C includes
118+C_INCLUDES = \
119+-ICore/Inc \
120+-IC:/Dev0/CubeRepo/STM32Cube_FW_F4_V1.25.1/Drivers/STM32F4xx_HAL_Driver/Inc \
121+-IC:/Dev0/CubeRepo/STM32Cube_FW_F4_V1.25.1/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy \
122+-IC:/Dev0/CubeRepo/STM32Cube_FW_F4_V1.25.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include \
123+-IC:/Dev0/CubeRepo/STM32Cube_FW_F4_V1.25.1/Drivers/CMSIS/Include \
124+-IC:/Dev0/CubeRepo/STM32Cube_FW_F4_V1.25.1/Drivers/CMSIS/Include
125+
126+
127+# compile gcc flags
128+ASFLAGS = $(MCU) $(AS_DEFS) $(AS_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections
129+
130+CFLAGS = $(MCU) $(C_DEFS) $(C_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections
131+
132+ifeq ($(DEBUG), 1)
133+CFLAGS += -g -gdwarf-2
134+endif
135+
136+
137+# Generate dependency information
138+CFLAGS += -MMD -MP -MF"$(@:%.o=%.d)"
139+
140+
141+#######################################
142+# LDFLAGS
143+#######################################
144+# link script
145+LDSCRIPT = STM32F429ZITx_FLASH.ld
146+
147+# libraries
148+LIBS = -lc -lm -lnosys
149+LIBDIR =
150+LDFLAGS = $(MCU) -specs=nano.specs -T$(LDSCRIPT) $(LIBDIR) $(LIBS) -Wl,-Map=$(BUILD_DIR)/$(TARGET).map,--cref -Wl,--gc-sections
151+
152+# default action: build all
153+all: $(BUILD_DIR)/$(TARGET).elf $(BUILD_DIR)/$(TARGET).hex $(BUILD_DIR)/$(TARGET).bin
154+
155+
156+#######################################
157+# build the application
158+#######################################
159+# list of objects
160+OBJECTS = $(addprefix $(BUILD_DIR)/,$(notdir $(C_SOURCES:.c=.o)))
161+vpath %.c $(sort $(dir $(C_SOURCES)))
162+# list of ASM program objects
163+OBJECTS += $(addprefix $(BUILD_DIR)/,$(notdir $(ASM_SOURCES:.s=.o)))
164+vpath %.s $(sort $(dir $(ASM_SOURCES)))
165+
166+$(BUILD_DIR)/%.o: %.c Makefile | $(BUILD_DIR)
167+ $(CC) -c $(CFLAGS) -Wa,-a,-ad,-alms=$(BUILD_DIR)/$(notdir $(<:.c=.lst)) $< -o $@
168+
169+$(BUILD_DIR)/%.o: %.s Makefile | $(BUILD_DIR)
170+ $(AS) -c $(CFLAGS) $< -o $@
171+
172+$(BUILD_DIR)/$(TARGET).elf: $(OBJECTS) Makefile
173+ $(CC) $(OBJECTS) $(LDFLAGS) -o $@
174+ $(SZ) $@
175+
176+$(BUILD_DIR)/%.hex: $(BUILD_DIR)/%.elf | $(BUILD_DIR)
177+ $(HEX) $< $@
178+
179+$(BUILD_DIR)/%.bin: $(BUILD_DIR)/%.elf | $(BUILD_DIR)
180+ $(BIN) $< $@
181+
182+$(BUILD_DIR):
183+ mkdir $@
184+
185+#######################################
186+# clean up
187+#######################################
188+clean:
189+ -rm -fR $(BUILD_DIR)
190+
191+#######################################
192+# dependencies
193+#######################################
194+-include $(wildcard $(BUILD_DIR)/*.d)
195+
196+# *** EOF ***
\ No newline at end of file
--- /dev/null
+++ b/gme_ws01/nuc-f429-blink/STM32F429ZITx_FLASH.ld
@@ -0,0 +1,209 @@
1+/*
2+******************************************************************************
3+**
4+
5+** File : LinkerScript.ld
6+**
7+** Author : Auto-generated by System Workbench for STM32
8+**
9+** Abstract : Linker script for STM32F429ZITx series
10+** 2048Kbytes FLASH and 256Kbytes RAM
11+**
12+** Set heap size, stack size and stack location according
13+** to application requirements.
14+**
15+** Set memory bank area and size if external memory is used.
16+**
17+** Target : STMicroelectronics STM32
18+**
19+** Distribution: The file is distributed “as is,” without any warranty
20+** of any kind.
21+**
22+*****************************************************************************
23+** @attention
24+**
25+** <h2><center>&copy; COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
26+**
27+** Redistribution and use in source and binary forms, with or without modification,
28+** are permitted provided that the following conditions are met:
29+** 1. Redistributions of source code must retain the above copyright notice,
30+** this list of conditions and the following disclaimer.
31+** 2. Redistributions in binary form must reproduce the above copyright notice,
32+** this list of conditions and the following disclaimer in the documentation
33+** and/or other materials provided with the distribution.
34+** 3. Neither the name of STMicroelectronics nor the names of its contributors
35+** may be used to endorse or promote products derived from this software
36+** without specific prior written permission.
37+**
38+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
39+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
40+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
41+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
42+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
43+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
44+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
45+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
46+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
47+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
48+**
49+*****************************************************************************
50+*/
51+
52+/* Entry Point */
53+ENTRY(Reset_Handler)
54+
55+/* Highest address of the user mode stack */
56+_estack = 0x20030000; /* end of RAM */
57+/* Generate a link error if heap and stack don't fit into RAM */
58+_Min_Heap_Size = 0x0; /* required amount of heap */
59+_Min_Stack_Size = 0x400; /* required amount of stack */
60+
61+/* Specify the memory areas */
62+MEMORY
63+{
64+RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 192K
65+CCMRAM (xrw) : ORIGIN = 0x10000000, LENGTH = 64K
66+FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 2048K
67+}
68+
69+/* Define output sections */
70+SECTIONS
71+{
72+ /* The startup code goes first into FLASH */
73+ .isr_vector :
74+ {
75+ . = ALIGN(4);
76+ KEEP(*(.isr_vector)) /* Startup code */
77+ . = ALIGN(4);
78+ } >FLASH
79+
80+ /* The program code and other data goes into FLASH */
81+ .text :
82+ {
83+ . = ALIGN(4);
84+ *(.text) /* .text sections (code) */
85+ *(.text*) /* .text* sections (code) */
86+ *(.glue_7) /* glue arm to thumb code */
87+ *(.glue_7t) /* glue thumb to arm code */
88+ *(.eh_frame)
89+
90+ KEEP (*(.init))
91+ KEEP (*(.fini))
92+
93+ . = ALIGN(4);
94+ _etext = .; /* define a global symbols at end of code */
95+ } >FLASH
96+
97+ /* Constant data goes into FLASH */
98+ .rodata :
99+ {
100+ . = ALIGN(4);
101+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
102+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
103+ . = ALIGN(4);
104+ } >FLASH
105+
106+ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
107+ .ARM : {
108+ __exidx_start = .;
109+ *(.ARM.exidx*)
110+ __exidx_end = .;
111+ } >FLASH
112+
113+ .preinit_array :
114+ {
115+ PROVIDE_HIDDEN (__preinit_array_start = .);
116+ KEEP (*(.preinit_array*))
117+ PROVIDE_HIDDEN (__preinit_array_end = .);
118+ } >FLASH
119+ .init_array :
120+ {
121+ PROVIDE_HIDDEN (__init_array_start = .);
122+ KEEP (*(SORT(.init_array.*)))
123+ KEEP (*(.init_array*))
124+ PROVIDE_HIDDEN (__init_array_end = .);
125+ } >FLASH
126+ .fini_array :
127+ {
128+ PROVIDE_HIDDEN (__fini_array_start = .);
129+ KEEP (*(SORT(.fini_array.*)))
130+ KEEP (*(.fini_array*))
131+ PROVIDE_HIDDEN (__fini_array_end = .);
132+ } >FLASH
133+
134+ /* used by the startup to initialize data */
135+ _sidata = LOADADDR(.data);
136+
137+ /* Initialized data sections goes into RAM, load LMA copy after code */
138+ .data :
139+ {
140+ . = ALIGN(4);
141+ _sdata = .; /* create a global symbol at data start */
142+ *(.data) /* .data sections */
143+ *(.data*) /* .data* sections */
144+
145+ . = ALIGN(4);
146+ _edata = .; /* define a global symbol at data end */
147+ } >RAM AT> FLASH
148+
149+ _siccmram = LOADADDR(.ccmram);
150+
151+ /* CCM-RAM section
152+ *
153+ * IMPORTANT NOTE!
154+ * If initialized variables will be placed in this section,
155+ * the startup code needs to be modified to copy the init-values.
156+ */
157+ .ccmram :
158+ {
159+ . = ALIGN(4);
160+ _sccmram = .; /* create a global symbol at ccmram start */
161+ *(.ccmram)
162+ *(.ccmram*)
163+
164+ . = ALIGN(4);
165+ _eccmram = .; /* create a global symbol at ccmram end */
166+ } >CCMRAM AT> FLASH
167+
168+
169+ /* Uninitialized data section */
170+ . = ALIGN(4);
171+ .bss :
172+ {
173+ /* This is used by the startup in order to initialize the .bss secion */
174+ _sbss = .; /* define a global symbol at bss start */
175+ __bss_start__ = _sbss;
176+ *(.bss)
177+ *(.bss*)
178+ *(COMMON)
179+
180+ . = ALIGN(4);
181+ _ebss = .; /* define a global symbol at bss end */
182+ __bss_end__ = _ebss;
183+ } >RAM
184+
185+ /* User_heap_stack section, used to check that there is enough RAM left */
186+ ._user_heap_stack :
187+ {
188+ . = ALIGN(8);
189+ PROVIDE ( end = . );
190+ PROVIDE ( _end = . );
191+ . = . + _Min_Heap_Size;
192+ . = . + _Min_Stack_Size;
193+ . = ALIGN(8);
194+ } >RAM
195+
196+
197+
198+ /* Remove information from the standard libraries */
199+ /DISCARD/ :
200+ {
201+ libc.a ( * )
202+ libm.a ( * )
203+ libgcc.a ( * )
204+ }
205+
206+ .ARM.attributes 0 : { *(.ARM.attributes) }
207+}
208+
209+
--- /dev/null
+++ b/gme_ws01/nuc-f429-blink/startup_stm32f429xx.s
@@ -0,0 +1,543 @@
1+/**
2+ ******************************************************************************
3+ * @file startup_stm32f429xx.s
4+ * @author MCD Application Team
5+ * @brief STM32F429xx Devices vector table for GCC based toolchains.
6+ * This module performs:
7+ * - Set the initial SP
8+ * - Set the initial PC == Reset_Handler,
9+ * - Set the vector table entries with the exceptions ISR address
10+ * - Branches to main in the C library (which eventually
11+ * calls main()).
12+ * After Reset the Cortex-M4 processor is in Thread mode,
13+ * priority is Privileged, and the Stack is set to Main.
14+ ******************************************************************************
15+ * @attention
16+ *
17+ * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
18+ * All rights reserved.</center></h2>
19+ *
20+ * This software component is licensed by ST under BSD 3-Clause license,
21+ * the "License"; You may not use this file except in compliance with the
22+ * License. You may obtain a copy of the License at:
23+ * opensource.org/licenses/BSD-3-Clause
24+ *
25+ ******************************************************************************
26+ */
27+
28+ .syntax unified
29+ .cpu cortex-m4
30+ .fpu softvfp
31+ .thumb
32+
33+.global g_pfnVectors
34+.global Default_Handler
35+
36+/* start address for the initialization values of the .data section.
37+defined in linker script */
38+.word _sidata
39+/* start address for the .data section. defined in linker script */
40+.word _sdata
41+/* end address for the .data section. defined in linker script */
42+.word _edata
43+/* start address for the .bss section. defined in linker script */
44+.word _sbss
45+/* end address for the .bss section. defined in linker script */
46+.word _ebss
47+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
48+
49+/**
50+ * @brief This is the code that gets called when the processor first
51+ * starts execution following a reset event. Only the absolutely
52+ * necessary set is performed, after which the application
53+ * supplied main() routine is called.
54+ * @param None
55+ * @retval : None
56+*/
57+
58+ .section .text.Reset_Handler
59+ .weak Reset_Handler
60+ .type Reset_Handler, %function
61+Reset_Handler:
62+ ldr sp, =_estack /* set stack pointer */
63+
64+/* Copy the data segment initializers from flash to SRAM */
65+ movs r1, #0
66+ b LoopCopyDataInit
67+
68+CopyDataInit:
69+ ldr r3, =_sidata
70+ ldr r3, [r3, r1]
71+ str r3, [r0, r1]
72+ adds r1, r1, #4
73+
74+LoopCopyDataInit:
75+ ldr r0, =_sdata
76+ ldr r3, =_edata
77+ adds r2, r0, r1
78+ cmp r2, r3
79+ bcc CopyDataInit
80+ ldr r2, =_sbss
81+ b LoopFillZerobss
82+/* Zero fill the bss segment. */
83+FillZerobss:
84+ movs r3, #0
85+ str r3, [r2], #4
86+
87+LoopFillZerobss:
88+ ldr r3, = _ebss
89+ cmp r2, r3
90+ bcc FillZerobss
91+
92+/* Call the clock system intitialization function.*/
93+ bl SystemInit
94+/* Call static constructors */
95+ bl __libc_init_array
96+/* Call the application's entry point.*/
97+ bl main
98+ bx lr
99+.size Reset_Handler, .-Reset_Handler
100+
101+/**
102+ * @brief This is the code that gets called when the processor receives an
103+ * unexpected interrupt. This simply enters an infinite loop, preserving
104+ * the system state for examination by a debugger.
105+ * @param None
106+ * @retval None
107+*/
108+ .section .text.Default_Handler,"ax",%progbits
109+Default_Handler:
110+Infinite_Loop:
111+ b Infinite_Loop
112+ .size Default_Handler, .-Default_Handler
113+/******************************************************************************
114+*
115+* The minimal vector table for a Cortex M3. Note that the proper constructs
116+* must be placed on this to ensure that it ends up at physical address
117+* 0x0000.0000.
118+*
119+*******************************************************************************/
120+ .section .isr_vector,"a",%progbits
121+ .type g_pfnVectors, %object
122+ .size g_pfnVectors, .-g_pfnVectors
123+
124+g_pfnVectors:
125+ .word _estack
126+ .word Reset_Handler
127+
128+ .word NMI_Handler
129+ .word HardFault_Handler
130+ .word MemManage_Handler
131+ .word BusFault_Handler
132+ .word UsageFault_Handler
133+ .word 0
134+ .word 0
135+ .word 0
136+ .word 0
137+ .word SVC_Handler
138+ .word DebugMon_Handler
139+ .word 0
140+ .word PendSV_Handler
141+ .word SysTick_Handler
142+
143+ /* External Interrupts */
144+ .word WWDG_IRQHandler /* Window WatchDog */
145+ .word PVD_IRQHandler /* PVD through EXTI Line detection */
146+ .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
147+ .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
148+ .word FLASH_IRQHandler /* FLASH */
149+ .word RCC_IRQHandler /* RCC */
150+ .word EXTI0_IRQHandler /* EXTI Line0 */
151+ .word EXTI1_IRQHandler /* EXTI Line1 */
152+ .word EXTI2_IRQHandler /* EXTI Line2 */
153+ .word EXTI3_IRQHandler /* EXTI Line3 */
154+ .word EXTI4_IRQHandler /* EXTI Line4 */
155+ .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
156+ .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
157+ .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
158+ .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
159+ .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
160+ .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
161+ .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
162+ .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
163+ .word CAN1_TX_IRQHandler /* CAN1 TX */
164+ .word CAN1_RX0_IRQHandler /* CAN1 RX0 */
165+ .word CAN1_RX1_IRQHandler /* CAN1 RX1 */
166+ .word CAN1_SCE_IRQHandler /* CAN1 SCE */
167+ .word EXTI9_5_IRQHandler /* External Line[9:5]s */
168+ .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
169+ .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
170+ .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
171+ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
172+ .word TIM2_IRQHandler /* TIM2 */
173+ .word TIM3_IRQHandler /* TIM3 */
174+ .word TIM4_IRQHandler /* TIM4 */
175+ .word I2C1_EV_IRQHandler /* I2C1 Event */
176+ .word I2C1_ER_IRQHandler /* I2C1 Error */
177+ .word I2C2_EV_IRQHandler /* I2C2 Event */
178+ .word I2C2_ER_IRQHandler /* I2C2 Error */
179+ .word SPI1_IRQHandler /* SPI1 */
180+ .word SPI2_IRQHandler /* SPI2 */
181+ .word USART1_IRQHandler /* USART1 */
182+ .word USART2_IRQHandler /* USART2 */
183+ .word USART3_IRQHandler /* USART3 */
184+ .word EXTI15_10_IRQHandler /* External Line[15:10]s */
185+ .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
186+ .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
187+ .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
188+ .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
189+ .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
190+ .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
191+ .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
192+ .word FMC_IRQHandler /* FMC */
193+ .word SDIO_IRQHandler /* SDIO */
194+ .word TIM5_IRQHandler /* TIM5 */
195+ .word SPI3_IRQHandler /* SPI3 */
196+ .word UART4_IRQHandler /* UART4 */
197+ .word UART5_IRQHandler /* UART5 */
198+ .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
199+ .word TIM7_IRQHandler /* TIM7 */
200+ .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
201+ .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
202+ .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
203+ .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
204+ .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
205+ .word ETH_IRQHandler /* Ethernet */
206+ .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
207+ .word CAN2_TX_IRQHandler /* CAN2 TX */
208+ .word CAN2_RX0_IRQHandler /* CAN2 RX0 */
209+ .word CAN2_RX1_IRQHandler /* CAN2 RX1 */
210+ .word CAN2_SCE_IRQHandler /* CAN2 SCE */
211+ .word OTG_FS_IRQHandler /* USB OTG FS */
212+ .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
213+ .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
214+ .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
215+ .word USART6_IRQHandler /* USART6 */
216+ .word I2C3_EV_IRQHandler /* I2C3 event */
217+ .word I2C3_ER_IRQHandler /* I2C3 error */
218+ .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
219+ .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
220+ .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
221+ .word OTG_HS_IRQHandler /* USB OTG HS */
222+ .word DCMI_IRQHandler /* DCMI */
223+ .word 0 /* Reserved */
224+ .word HASH_RNG_IRQHandler /* Hash and Rng */
225+ .word FPU_IRQHandler /* FPU */
226+ .word UART7_IRQHandler /* UART7 */
227+ .word UART8_IRQHandler /* UART8 */
228+ .word SPI4_IRQHandler /* SPI4 */
229+ .word SPI5_IRQHandler /* SPI5 */
230+ .word SPI6_IRQHandler /* SPI6 */
231+ .word SAI1_IRQHandler /* SAI1 */
232+ .word LTDC_IRQHandler /* LTDC_IRQHandler */
233+ .word LTDC_ER_IRQHandler /* LTDC_ER_IRQHandler */
234+ .word DMA2D_IRQHandler /* DMA2D */
235+
236+/*******************************************************************************
237+*
238+* Provide weak aliases for each Exception handler to the Default_Handler.
239+* As they are weak aliases, any function with the same name will override
240+* this definition.
241+*
242+*******************************************************************************/
243+ .weak NMI_Handler
244+ .thumb_set NMI_Handler,Default_Handler
245+
246+ .weak HardFault_Handler
247+ .thumb_set HardFault_Handler,Default_Handler
248+
249+ .weak MemManage_Handler
250+ .thumb_set MemManage_Handler,Default_Handler
251+
252+ .weak BusFault_Handler
253+ .thumb_set BusFault_Handler,Default_Handler
254+
255+ .weak UsageFault_Handler
256+ .thumb_set UsageFault_Handler,Default_Handler
257+
258+ .weak SVC_Handler
259+ .thumb_set SVC_Handler,Default_Handler
260+
261+ .weak DebugMon_Handler
262+ .thumb_set DebugMon_Handler,Default_Handler
263+
264+ .weak PendSV_Handler
265+ .thumb_set PendSV_Handler,Default_Handler
266+
267+ .weak SysTick_Handler
268+ .thumb_set SysTick_Handler,Default_Handler
269+
270+ .weak WWDG_IRQHandler
271+ .thumb_set WWDG_IRQHandler,Default_Handler
272+
273+ .weak PVD_IRQHandler
274+ .thumb_set PVD_IRQHandler,Default_Handler
275+
276+ .weak TAMP_STAMP_IRQHandler
277+ .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
278+
279+ .weak RTC_WKUP_IRQHandler
280+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
281+
282+ .weak FLASH_IRQHandler
283+ .thumb_set FLASH_IRQHandler,Default_Handler
284+
285+ .weak RCC_IRQHandler
286+ .thumb_set RCC_IRQHandler,Default_Handler
287+
288+ .weak EXTI0_IRQHandler
289+ .thumb_set EXTI0_IRQHandler,Default_Handler
290+
291+ .weak EXTI1_IRQHandler
292+ .thumb_set EXTI1_IRQHandler,Default_Handler
293+
294+ .weak EXTI2_IRQHandler
295+ .thumb_set EXTI2_IRQHandler,Default_Handler
296+
297+ .weak EXTI3_IRQHandler
298+ .thumb_set EXTI3_IRQHandler,Default_Handler
299+
300+ .weak EXTI4_IRQHandler
301+ .thumb_set EXTI4_IRQHandler,Default_Handler
302+
303+ .weak DMA1_Stream0_IRQHandler
304+ .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
305+
306+ .weak DMA1_Stream1_IRQHandler
307+ .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
308+
309+ .weak DMA1_Stream2_IRQHandler
310+ .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
311+
312+ .weak DMA1_Stream3_IRQHandler
313+ .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
314+
315+ .weak DMA1_Stream4_IRQHandler
316+ .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
317+
318+ .weak DMA1_Stream5_IRQHandler
319+ .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
320+
321+ .weak DMA1_Stream6_IRQHandler
322+ .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
323+
324+ .weak ADC_IRQHandler
325+ .thumb_set ADC_IRQHandler,Default_Handler
326+
327+ .weak CAN1_TX_IRQHandler
328+ .thumb_set CAN1_TX_IRQHandler,Default_Handler
329+
330+ .weak CAN1_RX0_IRQHandler
331+ .thumb_set CAN1_RX0_IRQHandler,Default_Handler
332+
333+ .weak CAN1_RX1_IRQHandler
334+ .thumb_set CAN1_RX1_IRQHandler,Default_Handler
335+
336+ .weak CAN1_SCE_IRQHandler
337+ .thumb_set CAN1_SCE_IRQHandler,Default_Handler
338+
339+ .weak EXTI9_5_IRQHandler
340+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
341+
342+ .weak TIM1_BRK_TIM9_IRQHandler
343+ .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
344+
345+ .weak TIM1_UP_TIM10_IRQHandler
346+ .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
347+
348+ .weak TIM1_TRG_COM_TIM11_IRQHandler
349+ .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
350+
351+ .weak TIM1_CC_IRQHandler
352+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
353+
354+ .weak TIM2_IRQHandler
355+ .thumb_set TIM2_IRQHandler,Default_Handler
356+
357+ .weak TIM3_IRQHandler
358+ .thumb_set TIM3_IRQHandler,Default_Handler
359+
360+ .weak TIM4_IRQHandler
361+ .thumb_set TIM4_IRQHandler,Default_Handler
362+
363+ .weak I2C1_EV_IRQHandler
364+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
365+
366+ .weak I2C1_ER_IRQHandler
367+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
368+
369+ .weak I2C2_EV_IRQHandler
370+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
371+
372+ .weak I2C2_ER_IRQHandler
373+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
374+
375+ .weak SPI1_IRQHandler
376+ .thumb_set SPI1_IRQHandler,Default_Handler
377+
378+ .weak SPI2_IRQHandler
379+ .thumb_set SPI2_IRQHandler,Default_Handler
380+
381+ .weak USART1_IRQHandler
382+ .thumb_set USART1_IRQHandler,Default_Handler
383+
384+ .weak USART2_IRQHandler
385+ .thumb_set USART2_IRQHandler,Default_Handler
386+
387+ .weak USART3_IRQHandler
388+ .thumb_set USART3_IRQHandler,Default_Handler
389+
390+ .weak EXTI15_10_IRQHandler
391+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
392+
393+ .weak RTC_Alarm_IRQHandler
394+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
395+
396+ .weak OTG_FS_WKUP_IRQHandler
397+ .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
398+
399+ .weak TIM8_BRK_TIM12_IRQHandler
400+ .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
401+
402+ .weak TIM8_UP_TIM13_IRQHandler
403+ .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
404+
405+ .weak TIM8_TRG_COM_TIM14_IRQHandler
406+ .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
407+
408+ .weak TIM8_CC_IRQHandler
409+ .thumb_set TIM8_CC_IRQHandler,Default_Handler
410+
411+ .weak DMA1_Stream7_IRQHandler
412+ .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
413+
414+ .weak FMC_IRQHandler
415+ .thumb_set FMC_IRQHandler,Default_Handler
416+
417+ .weak SDIO_IRQHandler
418+ .thumb_set SDIO_IRQHandler,Default_Handler
419+
420+ .weak TIM5_IRQHandler
421+ .thumb_set TIM5_IRQHandler,Default_Handler
422+
423+ .weak SPI3_IRQHandler
424+ .thumb_set SPI3_IRQHandler,Default_Handler
425+
426+ .weak UART4_IRQHandler
427+ .thumb_set UART4_IRQHandler,Default_Handler
428+
429+ .weak UART5_IRQHandler
430+ .thumb_set UART5_IRQHandler,Default_Handler
431+
432+ .weak TIM6_DAC_IRQHandler
433+ .thumb_set TIM6_DAC_IRQHandler,Default_Handler
434+
435+ .weak TIM7_IRQHandler
436+ .thumb_set TIM7_IRQHandler,Default_Handler
437+
438+ .weak DMA2_Stream0_IRQHandler
439+ .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
440+
441+ .weak DMA2_Stream1_IRQHandler
442+ .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
443+
444+ .weak DMA2_Stream2_IRQHandler
445+ .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
446+
447+ .weak DMA2_Stream3_IRQHandler
448+ .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
449+
450+ .weak DMA2_Stream4_IRQHandler
451+ .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
452+
453+ .weak ETH_IRQHandler
454+ .thumb_set ETH_IRQHandler,Default_Handler
455+
456+ .weak ETH_WKUP_IRQHandler
457+ .thumb_set ETH_WKUP_IRQHandler,Default_Handler
458+
459+ .weak CAN2_TX_IRQHandler
460+ .thumb_set CAN2_TX_IRQHandler,Default_Handler
461+
462+ .weak CAN2_RX0_IRQHandler
463+ .thumb_set CAN2_RX0_IRQHandler,Default_Handler
464+
465+ .weak CAN2_RX1_IRQHandler
466+ .thumb_set CAN2_RX1_IRQHandler,Default_Handler
467+
468+ .weak CAN2_SCE_IRQHandler
469+ .thumb_set CAN2_SCE_IRQHandler,Default_Handler
470+
471+ .weak OTG_FS_IRQHandler
472+ .thumb_set OTG_FS_IRQHandler,Default_Handler
473+
474+ .weak DMA2_Stream5_IRQHandler
475+ .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
476+
477+ .weak DMA2_Stream6_IRQHandler
478+ .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
479+
480+ .weak DMA2_Stream7_IRQHandler
481+ .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
482+
483+ .weak USART6_IRQHandler
484+ .thumb_set USART6_IRQHandler,Default_Handler
485+
486+ .weak I2C3_EV_IRQHandler
487+ .thumb_set I2C3_EV_IRQHandler,Default_Handler
488+
489+ .weak I2C3_ER_IRQHandler
490+ .thumb_set I2C3_ER_IRQHandler,Default_Handler
491+
492+ .weak OTG_HS_EP1_OUT_IRQHandler
493+ .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
494+
495+ .weak OTG_HS_EP1_IN_IRQHandler
496+ .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
497+
498+ .weak OTG_HS_WKUP_IRQHandler
499+ .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
500+
501+ .weak OTG_HS_IRQHandler
502+ .thumb_set OTG_HS_IRQHandler,Default_Handler
503+
504+ .weak DCMI_IRQHandler
505+ .thumb_set DCMI_IRQHandler,Default_Handler
506+
507+ .weak HASH_RNG_IRQHandler
508+ .thumb_set HASH_RNG_IRQHandler,Default_Handler
509+
510+ .weak FPU_IRQHandler
511+ .thumb_set FPU_IRQHandler,Default_Handler
512+
513+ .weak UART7_IRQHandler
514+ .thumb_set UART7_IRQHandler,Default_Handler
515+
516+ .weak UART8_IRQHandler
517+ .thumb_set UART8_IRQHandler,Default_Handler
518+
519+ .weak SPI4_IRQHandler
520+ .thumb_set SPI4_IRQHandler,Default_Handler
521+
522+ .weak SPI5_IRQHandler
523+ .thumb_set SPI5_IRQHandler,Default_Handler
524+
525+ .weak SPI6_IRQHandler
526+ .thumb_set SPI6_IRQHandler,Default_Handler
527+
528+ .weak SAI1_IRQHandler
529+ .thumb_set SAI1_IRQHandler,Default_Handler
530+
531+ .weak LTDC_IRQHandler
532+ .thumb_set LTDC_IRQHandler,Default_Handler
533+
534+ .weak LTDC_ER_IRQHandler
535+ .thumb_set LTDC_ER_IRQHandler,Default_Handler
536+
537+ .weak DMA2D_IRQHandler
538+ .thumb_set DMA2D_IRQHandler,Default_Handler
539+
540+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
541+
542+
543+
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