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專案描述

By simulator + Tcl + C language, let's verify ASIC and FPGA effectively!

(simulator <= DPI-C => C++, simulator <= named pipes => C++ are under development, too.)

NOODLYBOX is a mimic processor for verification.

It can manipulate FPGA model which is connected to microcomputer's local bus.

Detail:

  1. A microcomputer and FPGA are mounted on a printed circuit board.
  2. A microcomputer and the connection form between FPGA are SRAM interface.
  3. FPGA is modeled by VHDL or Verilog.
  4. ModelSim, ISE Simulator, or Icarus Verilog are installed.

When all the conditions mentioned above are met, NOODLBOX can act as the substitute of the microcomputer on an HDL simulator.

System Requirements

System requirement is not defined

發布 2008-11-09 00:09
noodlybox 0002 (1 files 隱藏)

發布版本通知

NOODLYBOXの2回目のリリースです。
Repositoryのtrunk rev44に相当します。

Verilog HDLでシミュレーションが行えるようになりました。
サンプルのFPGAデザインも、Verilog HDLで書いたものを追加してあります。

更動紀錄

機能リクエスト
#13875 Verilog HDLに移植する

バグ修正
#13916 DIVIDEが1でないときMIMIC_PLLが不正な動作をする