專案描述

HDLmaker generates hierarchical Verilog and VHDL code, PCB netlists, simulation and synthesis scripts/projects/make files, and schematics. It can translate Verilog/VHDL and HDLmaker projects into HTML, including extensive hyperlinking between the modules. It can also translate PADS PCB netlists into Verilog and VHDL and can do some simple VHDL to Verilog translations. HDLMaker synplifies the development of complex FPGAs and ASICs, and has extensive support for most Xilinx FPGAs.

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