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專案描述

Confluence is a functional programming language for reactive system design, including FPGAs, ASICs, and hard-real-time software. Confluence system descriptions have a large information to linecount ratio. It is typically two to five times more compact than Verilog. Confluence can compile a single body of source code into to Verilog, VHDL, C, and NuSMV.

System Requirements

System requirement is not defined
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2005-02-02 05:41 Back to release list
0.10.2

Adds a new code generator that allows it to compile into JHDL, a Java-based hardware description language.
標籤: Major feature enhancements

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