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專案描述

Confluence is a functional programming language for reactive system design, including FPGAs, ASICs, and hard-real-time software. Confluence system descriptions have a large information to linecount ratio. It is typically two to five times more compact than Verilog. Confluence can compile a single body of source code into to Verilog, VHDL, C, and NuSMV.

System Requirements

System requirement is not defined
Information regarding Project Releases and Project Resources. Note that the information here is a quote from Freecode.com page, and the downloads themselves may not be hosted on OSDN.

2005-02-18 05:43
0.10.3

This release includes the initial FNF C model generator that
enables a compilation path from Confluence to C. New
features include a new simulator data structure, which
enables
running multiple simulation models at once, and provides
access to all hierarchical named signals in a design.
This release also includes the Icarus Verilog FNF
generator, providing a path from Verilog to C, VHDL, NuSMV,
and JHDL.
標籤: Major feature enhancements

2005-02-02 05:41
0.10.2

Adds a new code generator that allows it to compile into JHDL, a Java-based hardware description language.
標籤: Major feature enhancements

2005-01-09 10:57
0.10.0

In this release, the compiler backend was integrated with
FNF, forming a clean partition between language evaluation
and model generation.
標籤: Major feature enhancements

Project Resources